Flash Memory. M25P40 Datasheet
4 Mbit, Low Voltage, Serial Flash Memory
With 25 MHz SPI Bus Interface
s 4 Mbit of Flash Memory
s Page Program (up to 256 Bytes) in 1.5ms
s Sector Erase (512 Kbit) in 2 s (typical)
s Bulk Erase (4 Mbit) in 5 s (typical)
s 2.7 V to 3.6 V Single Supply Voltage
s SPI Bus Compatible Serial Interface
s 25 MHz Clock Rate (maximum)
s Deep Power-down Mode 1 µA (typical)
s Electronic Signature (12h)
s More than 100,000 Erase/Program Cycles per
s More than 20 Year Data Retention
Figure 1. Packages
150 mil width
The M25P40 is a 4 Mbit (512K x 8) Serial Flash
Memory, with advanced write protection mecha-
nisms, accessed by a high speed SPI-compatible
The memory can be programmed 1 to 256 bytes at
a time, using the Page Program instruction.
The memory is organized as 8 sectors, each con-
taining 256 pages. Each page is 256 bytes wide.
Thus, the whole memory can be viewed as con-
sisting of 2048 pages, or 524,288 bytes.
The whole memory can be erased using the Bulk
Erase instruction, or a sector at a time, using the
Sector Erase instruction.
Figure 2. Logic Diagram
Figure 3. SO and VFQFPN Connections
Note: 1. See page 31 (onwards) for package dimensions, and how
to identify pin-1.
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
VCC Supply Voltage
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be pro-
grammed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Pro-
gram, Erase or Write Status Register cycle is in
progress, the device will be in the Standby mode
(this is not the Deep Power-down mode). Driving
Chip Select (S) Low enables the device, placing it
in the active power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against program or erase
instructions (as specified by the values in the BP2,
BP1 and BP0 bits of the Status Register).