W196 Datasheet: Spread Spectrum FTG for 440BX and VIA Apollo Pro-133





W196 Spread Spectrum FTG for 440BX and VIA Apollo Pro-133 Datasheet

Part Number W196
Description Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
Manufacture Cypress Semiconductor
Total Page 11 Pages
PDF Download Download W196 Datasheet PDF

Features: PRELIMINARY W196 Spread Spectrum FTG f or 440BX and VIA Apollo Pro-133 Feature s • Maximized EMI suppression using C ypress’s Spread Spectrum Technology System frequency synthesizer for 440 BX, 440ZX, and VIA Apollo Pro-133 • I 2C programmable to 155 MHz (32 selectab le frequencies) • Two skew-controlled copies of CPU output • Seven copies of PCI output (synchronous w/CPU output ) • One copy of 14.31818-MHz IOAPIC o utput • One copy of 48-MHz USB output • Selectable 24-/48-MHz clock is det ermined by resistor straps on power up • One high-drive output buffer that p roduces a copy of the 14.318-MHz refere nce • Isolated core VDD pin for noise reduction CPU Cycle to Cycle Jitter: . ....................................... .. 250 ps CPU, PCI Output Edge Rate: .. ....................................... ≥1 V/ns CPU0:1 Output Skew: ........ ....................................... . 175 ps PCI_F, PCI1:6 Output Skew: ... ....................................500 ps CPU to PCI Skew: ........................ 1..

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PRELIMINARY
W196
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• System frequency synthesizer for 440BX, 440ZX, and
VIA Apollo Pro-133
• I2C programmable to 155 MHz (32 selectable
frequencies)
• Two skew-controlled copies of CPU output
• Seven copies of PCI output (synchronous w/CPU out-
put)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz clock is determined by resistor
straps on power up
• One high-drive output buffer that produces a copy of
the 14.318-MHz reference
• Isolated core VDD pin for noise reduction
Key Specifications
Supply Voltages: ....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
VDDQ3
REF2X/SEL48#
GND
VDDQ3
IOAPIC
FS1 PLL 1
FS0
÷2/÷3
SDATA
SCLOCK
I2C
LOGIC
VDDQ2
CPU0
CPU1
GND
VDDQ3
PCI_F
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
GND
CPU Cycle to Cycle Jitter: .......................................... 250 ps
CPU, PCI Output Edge Rate: ......................................... ≥1 V/ns
CPU0:1 Output Skew: ................................................ 175 ps
PCI_F, PCI1:6 Output Skew: .......................................500 ps
CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads)
REF2X/SEL48#, SCLOCK, SDATA: ............... 250-kpull-up
FS1: ............................................................250-kpull-down
FS0: ...................................................No pull-up or pull-down
Note: Internal pull-up or pull-down resistors should not be re-
lied upon for setting I/O pins HIGH or LOW.
Table 1. Pin Selectable Frequency
FS1 FS0 CPU(0:1) PCI
1 1 133.3 MHz 33.3 MHz
1
0
105 MHz
35 MHz
0
1
100 MHz
33.3 MHz
0 0 66.8 MHz 33.3 MHz
Pin Configuration
X1
X2
GND
PCI_F
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
PCI6
VDDQ3
48MHz
24_48MHz/FS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 GND
27 REF2X/SEL48#
26 VDDQ3
25 VDDQ2
24 IOAPIC
23 VDDQ2
22 CPU0
21 CPU1
20 VDDQ3
19 GND
18 SDATA
17 SCLOCK
16 FS0
15 GND
PLL2
VDDQ3
48MHz
24_48MHz/FS1
GND
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 28, 1999, rev. **

                    
           






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