NOR Gate. MM74HC02 Datasheet


MM74HC02 Gate. Datasheet pdf. Equivalent


MM74HC02


Quad 2-Input NOR Gate
MM74HC02 Quad 2-Input NOR Gate

September 1983 Revised February 1999

MM74HC02 Quad 2-Input NOR Gate
General Description
The MM74HC02 NOR gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs, providing high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

Features
s Typical propagation delay: 8 ns s Wide power supply range: 2–6V s Low quiescent supply current: 20 µA maximum (74HC Series) s Low input current: 1 µA maximum s High output current: 4 mA minimum

Ordering Code:
Order Number MM74HC02M MM74HC02SJ MM74HC02MTC MM74HC02N Package Number M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.)

Co...



MM74HC02
September 1983
Revised February 1999
MM74HC02
Quad 2-Input NOR Gate
General Description
The MM74HC02 NOR gates utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low power consumption of standard
CMOS integrated circuits. All gates have buffered outputs,
providing high noise immunity and the ability to drive 10
LS-TTL loads. The 74HC logic family is functionally as well
as pin-out compatible with the standard 74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to VCC and ground.
Features
s Typical propagation delay: 8 ns
s Wide power supply range: 2–6V
s Low quiescent supply current: 20 µA maximum
(74HC Series)
s Low input current: 1 µA maximum
s High output current: 4 mA minimum
Ordering Code:
Order Number Package Number
Package Description
MM74HC02M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
MM74HC02SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC02MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC02N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.)
Connection Diagram
Pin Assignment for DIP, SOIC, SOP and TSSOP
Logic Diagram
Top View
© 1999 Fairchild Semiconductor Corporation DS005294.prf
www.fairchildsemi.com

MM74HC02
Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IOUT)
DC VCC or GND Current, per pin
(ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S.O. Package only
Lead Temperature (TL)
(Soldering 10 seconds)
0.5 to +7.0V
1.5 to VCC +1.5V
0.5 to VCC +0.5V
±20 mA
±25 mA
±50 mA
65°C to +150°C
600 mW
500 mW
260°C
Recommended Operating
Conditions
Min Max Units
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature Range (TA)
Input Rise or Fall Times
2
0
40
6
VCC
+125
V
V
°C
(tr, tf) VCC = 2.0V
1000 ns
VCC = 4.5V
500 ns
VCC = 6.0V
400 ns
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package:
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TA = 25°C
TA = −40 to 85°C TA = −40 to 125°C Units
Typ Guaranteed Limits
VIH Minimum HIGH Level
Input Voltage
2.0V
4.5V
1.5 1.5
3.15 3.15
1.5
3.15
V
V
6.0V
4.2 4.2
4.2 V
VIL Maximum LOW Level
Input Voltage
2.0V
4.5V
0.5 0.5
1.35 1.35
0.5
1.35
V
V
6.0V
1.8 1.8
1.8 V
VOH
Minimum HIGH Level
VIN = VIL
Output Voltage
|IOUT| 20 µA
2.0V
4.5V
2.0
4.5
1.9
4.4
1.9
4.4
1.9 V
4.4 V
6.0V
6.0
5.9
5.9
5.9 V
VIN = VIL
|IOUT| 4.0 mA
|IOUT| 5.2 mA
VOL
Maximum LOW Level
VIN = VIH or VIL
Output Voltage
|IOUT| 20 µA
4.5V 4.2 3.98
6.0V 5.7 5.48
2.0V
4.5V
0
0
0.1
0.1
3.84
5.34
0.1
0.1
3.7 V
5.2 V
0.1 V
0.1 V
6.0V
0
0.1
0.1
0.1 V
IIN Maximum Input
Current
VIN = VIH or VIL
|IOUT| 4.0 mA
|IOUT| 5.2 mA
VIN = VCC or GND
4.5V 0.2 0.26
6.0V 0.2 0.26
6.0V
±0.1
0.33
0.33
±1.0
0.4
0.4
±1.0
V
V
µA
ICC Maximum Quiescent VIN = VCC or GND
6.0V
2.0 20
40 µA
Supply Current
IOUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current
(IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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