1-of-8 Decoder/Demultiplexer. SN74LS138 Datasheet

SN74LS138 Decoder/Demultiplexer. Datasheet pdf. Equivalent

Part SN74LS138
Description 1-of-8 Decoder/Demultiplexer
Feature SN74LS138 1−of−8 Decoder/ Demultiplexer The LSTTL/MSI SN74LS138 is a high speed 1-of-8 Decoder/ Dem.
Manufacture ON Semiconductor
Datasheet
Download SN74LS138 Datasheet



SN74LS138
SN74LS138
1−of−8 Decoder/
Demultiplexer
The LSTTL/MSI SN74LS138 is a high speed 1-of-8 Decoder/
Demultiplexer. This device is ideally suited for high speed bipolar
memory chip select address decoding. The multiple input enables
allow parallel expansion to a 1-of-24 decoder using just three LS138
devices or to a 1-of-32 decoder using four LS138s and one inverter.
The LS138 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all ON Semiconductor
TTL families.
Demultiplexing Capability
Multiple Input Enable for Easy Expansion
Typical Power Dissipation of 32 mW
Active Low Mutually Exclusive Outputs
Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current High
IOL Output Current Low
0.4
8.0
mA
mA
http://onsemi.com
LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
© Semiconductor Components Industries, LLC, 2006
June, 2006 Rev. 8
16
1
SOEIAJ
M SUFFIX
CASE 966
ORDERING INFORMATION
Device
Package
Shipping
SN74LS138N
16 Pin DIP 2000 Units/Box
SN74LS138D
SOIC16
38 Units/Rail
SN74LS138DR2 SOIC16 2500/Tape & Reel
SN74LS138M
SOEIAJ16
See Note 1
SN74LS138MEL SOEIAJ16
See Note 1
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
1 Publication Order Number:
SN74LS138/D



SN74LS138
SN74LS138
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC O0 O1 O2 O3 O4 O5 O6
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1 2 3 4 56 78
A0 A1 A2 E1 E2 E3 O7 GND
PIN NAMES
A0 − A2
E1, E2
E3
O0 − O7
Address Inputs
Enable (Active LOW) Inputs
Enable (Active HIGH) Input
Active LOW Outputs
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOGIC SYMBOL
123
456
1 23
A0 A1 A2
E
O0 O1 O2 O3 O4 O5 O6 O7
15 14 13 12 11 10 9 7
VCC = PIN 16
GND = PIN 8
LOGIC DIAGRAM
A2 A1
A0
32
1
E1 E2 E3
45
6
VCC = PIN 16
GND = PIN 8
= Pin Numbers
7
O7
9 10 11 12 13 14 15
O6 O5 O4 O3 O2 O1 O0
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2





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