SN74LS175 SCHOTTKY Datasheet

SN74LS175 Datasheet, PDF, Equivalent


Part Number

SN74LS175

Description

LOW POWER SCHOTTKY

Manufacture

ON Semiconductor

Total Page 8 Pages
Datasheet
Download SN74LS175 Datasheet


SN74LS175
SN74LS175
Quad D Flip-Flop
The LSTTL / MSI SN74LS175 is a high speed Quad D Flip-Flop.
The device is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D inputs is
stored during the LOW to HIGH clock transition. Both true and
complemented outputs of each flip-flop are provided. A Master Reset
input resets all flip-flops, independent of the Clock or D inputs, when
LOW.
The LS175 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all ON Semiconductor
TTL families.
Edge-Triggered D-Type Inputs
Buffered-Positive Edge-Triggered Clock
Clock to Output Delays of 30 ns
Asynchronous Common Reset
True and Complement Output
Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current – High
IOL Output Current – Low
– 0.4
8.0
mA
mA
http://onsemi.com
LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
Shipping
SN74LS175N 16 Pin DIP 2000 Units/Box
SN74LS175D
16 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1
Publication Order Number:
SN74LS175/D

SN74LS175
SN74LS175
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q3 Q3 D3 D2 Q2 Q2 CP
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1 2 3 4 56 78
MR Q0 Q0 D0 D1 Q1 Q1 GND
PIN NAMES
D0 – D3
CP
MR
Q0 – Q3
Q0 – Q3
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
True Outputs
Complemented Outputs
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
5 U.L.
LOGIC SYMBOL
4 5 12 13
D0 D1 D2 D3
9 CP
1 MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
MR CP D3
1 9 13
3 2 6 7 11 10 14 15
VCC = PIN 16
GND = PIN 8
LOGIC DIAGRAM
D2 D1
12 5
D0
4
DQ
CP Q
CD
DQ
CP Q
CD
DQ
CP Q
CD
DQ
CP Q
CD
14 15
Q3 Q3
11 10
Q2 Q2
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
67
Q1 Q1
32
Q0 Q0
http://onsemi.com
2


Features SN74LS175 Quad D Flip-Flop The LSTTL / M SI SN74LS175 is a high speed Quad D Fli p-Flop. The device is useful for genera l flip-flop requirements where clock an d clear inputs are common. The informat ion on the D inputs is stored during th e LOW to HIGH clock transition. Both tr ue and complemented outputs of each fli p-flop are provided. A Master Reset inp ut resets all flip-flops, independent o f the Clock or D inputs, when LOW. The LS175 is fabricated with the Schottky b arrier diode process for high speed and is completely compatible with all ON S emiconductor TTL families. http://onse mi.com • • • • • • LOW PO WER SCHOTTKY Edge-Triggered D-Type Inp uts Buffered-Positive Edge-Triggered Cl ock Clock to Output Delays of 30 ns Asy nchronous Common Reset True and Complem ent Output Input Clamp Diodes Limit Hig h Speed Termination Effects 16 1 GUARA NTEED OPERATING RANGES Symbol VCC TA IO H IOL Parameter Supply Voltage Operatin g Ambient Temperature Range Output Current – High Output Current – Low Min .
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