m Preliminary PLL650-04 o c . EMI Clock for 10/100 PHY and Gigabit Ethernet Low U t4 e FEATURES PIN CONFIGURATION e hswing with 25-mA output drive Full CMOS output S capability at TTL level. a t Advanced, low power, sub-micron CMOS processes. a 25 MHz .D fundamental crystal or clock input. Low jitter (< 80ps cycle-to-cycle) w 25 MHz and 50 MHz outp...
