256Mb DDR SDRAM
CAS Latency and Frequency
Maximum Operating Frequency (MHz)
• Double data rate architecture: two data transfers per
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• SSTL_2 compatible I/O interface
• VDDQ = 2.6V ± 0.1V
• VDD = 2.6V ± 0.1V
• Lead-free and Halogen-free product available
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic
tion may be enabled to provide a self-timed row precharge
random-access memory containing 268,435,456 bits. It is
that is initiated at the end of the burst access.
internally configured as a quad-bank DRAM.
As with standard SDRAMs, the pipelined, multibank architec-
The 256Mb DDR SDRAM uses a double-data-rate architec-
ture of DDR SDRAMs allows for concurrent operation,
ture to achieve high-speed operation. The double data rate
thereby providing high effective bandwidth by hiding row pre-
architecture is essentially a 2n prefetch architecture with an
charge and activation time.
ianttethrefaIc/eOdpeinssig.nAedsintoglterarnesafderotrwworditaetaacwcoersdssfopretrhcelo2c5Dk6acMytabcSleheet4AUn.acuotmo refresh mode is provided along with a power-saving DataShee
DDR SDRAM effectively consists of a single 2n-bit wide, one Power Down mode. All inputs are compatible with the JEDEC
clock cycle data transfer at the internal DRAM core and two
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
corresponding n-bit wide, one-half-clock-cycle data transfers patible.
at the I/O pins.
The functionality described and the timing specifications
A bidirectional data strobe (DQS) is transmitted externally,
included in this data sheet are for the DLL Enabled mode
along with data, for use in data capture at the receiver. DQS of operation.
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
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