EXCLUSIVE Gate. 74AUP2G86 Datasheet

74AUP2G86 Gate. Datasheet pdf. Equivalent


Part 74AUP2G86
Description Low Power Dual 2-Input EXCLUSIVE Gate
Feature 74AUP2G86 Low-power dual 2-input EXCLUSIVE-OR gate Rev. 8 — 24 January 2013 Product data sheet 1.
Manufacture NXP
Datasheet
Download 74AUP2G86 Datasheet


74AUP2G86 Low-power dual 2-input EXCLUSIVE-OR gate Rev. 8 74AUP2G86 Datasheet
NEW PRODUCT 74AUP2G86 DUAL EXCLUSIVE OR GATE Description 74AUP2G86 Datasheet
74AUP2G86 Low-power dual 2-input EXCLUSIVE-OR gate Rev. 9 74AUP2G86 Datasheet
Recommendation Recommendation Datasheet 74AUP2G86 Datasheet




74AUP2G86
74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
Rev. 8 — 24 January 2013
Product data sheet
1. General description
The 74AUP2G86 provides the dual 2-input EXCLUSIVE-OR function.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 A (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C



74AUP2G86
NXP Semiconductors
74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP2G86DC 40 C to +125 C VSSOP8
74AUP2G86GT 40 C to +125 C XSON8
74AUP2G86GF 40 C to +125 C XSON8
74AUP2G86GD 40 C to +125 C XSON8
74AUP2G86GM 40 C to +125 C XQFN8
74AUP2G86GN 40 C to +125 C XSON8
74AUP2G86GS 40 C to +125 C XSON8
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 1.95 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 1 0.5 mm
SOT1089
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3 2 0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 1.6 0.5 mm
SOT902-2
extremely thin small outline package; no leads;
8 terminals; body 1.2 1.0 0.35 mm
SOT1116
extremely thin small outline package; no leads;
8 terminals; body 1.35 1.0 0.35 mm
SOT1203
4. Marking
Table 2. Marking codes
Type number
74AUP2G86DC
74AUP2G86GT
74AUP2G86GF
74AUP2G86GT
74AUP2G86GM
74AUP2G86GN
74AUP2G86GS
Marking code[1]
p86
p86
pH
p86
p86
pH
pH
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1A
1Y
1B
2A 2Y
2B
001aah760
Fig 1. Logic symbol
=1
=1
001aah761
Fig 2. IEC logic symbol
74AUP2G86
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 24 January 2013
© NXP B.V. 2013. All rights reserved.
2 of 21







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)