NAND gate. 74AUP2G00 Datasheet

74AUP2G00 gate. Datasheet pdf. Equivalent

Part 74AUP2G00
Description Low-power dual 2-input NAND gate
Feature 74AUP2G00 Low-power dual 2-input NAND gate Rev. 8 — 5 February 2013 Product data sheet 1. General .
Manufacture NXP
Datasheet
Download 74AUP2G00 Datasheet

74AUP2G00 Low-power dual 2-input NAND gate Rev. 8 — 5 Februa 74AUP2G00 Datasheet
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74AUP2G00
74AUP2G00
Low-power dual 2-input NAND gate
Rev. 8 — 5 February 2013
Product data sheet
1. General description
The 74AUP2G00 provides dual 2-input NAND function.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1 000 V
Low static power consumption; ICC = 0.9 A (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C



74AUP2G00
NXP Semiconductors
74AUP2G00
Low-power dual 2-input NAND gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name Description
74AUP2G00DC
40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
74AUP2G00GT
40 C to +125 C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 1.95 0.5 mm
74AUP2G00GF
40 C to +125 C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 1 0.5 mm
74AUP2G00GD
40 C to +125 C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 3 2 0.5 mm
74AUP2G00GM
40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 1.6 0.5 mm
74AUP2G00GN
40 C to +125 C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.2 1.0 0.35 mm
74AUP2G00GS
40 C to +125 C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 1.0 0.35 mm
Version
SOT765-1
SOT833-1
SOT1089
SOT996-2
SOT902-2
SOT1116
SOT1203
4. Marking
Table 2. Marking codes
Type number
74AUP2G00DC
74AUP2G00GT
74AUP2G00GF
74AUP2G00GD
74AUP2G00GM
74AUP2G00GN
74AUP2G00GS
Marking code[1]
p00
p00
pA
p00
p00
pA
pA
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1A
1Y
1B
2A
2Y
2B
001aah748
Fig 1. Logic symbol
&
&
001aah749
Fig 2. IEC logic symbol
B
Y
A
mna099
Fig 3. Logic diagram (one gate)
74AUP2G00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 5 February 2013
© NXP B.V. 2013. All rights reserved.
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