74LVT16646 Transceiver/Register Datasheet

74LVT16646 Datasheet, PDF, Equivalent


Part Number

74LVT16646

Description

Low Voltage 16-Bit Transceiver/Register

Manufacture

Fairchild Semiconductor

Total Page 9 Pages
Datasheet
Download 74LVT16646 Datasheet


74LVT16646
www.DataSheet4U.com
January 2000
Revised October 2001
74LVT16646 74LVTH16646
Low Voltage 16-Bit Transceiver/Register
with 3-STATE Outputs
General Description
The LVT16646 and LVTH16646 contains sixteen non-
inverting bidirectional registered bus transceivers providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Each byte has sepa-
rate control inputs which can be shorted together for full
16-bit operation. The DIR inputs determine the direction of
data flow through the device. The CPAB and CPBA inputs
load data into the registers on the LOW-to-HIGH transition
(see Functional Description).
The LVTH16646 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These transceivers are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT16646 and
LVTH16646 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16646)
s Also available without bushold feature (74LVT16646)
s Live insertion/extraction permitted
s Power Up/Down high impedance provides
glitch-free bus loading
s Outputs source/sink 32 mA/+64 mA
s Latch-up conforms to JEDEC JED78
s ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
Ordering Code:
Order Number Package Number
Package Description
74LVT16646MEA
(Preliminary)
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16646MTD
(Preliminary)
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16646MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16646MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS012023
www.fairchildsemi.com

74LVT16646
Connection Diagram
Pin Descriptions
Pin Names
Description
A0A15
Data Register A Inputs/3-STATE Outputs
B0B15
Data Register B Inputs/3-STATE Outputs
CPABn, CPBAn Clock Pulse Inputs
SABn, SBAn
Select Inputs
OE1, OE2
Output Enable Inputs
DIRn
Direction Control Inputs
Truth Table
(Note 1)
OE1
Inputs
DIR1 CPAB1 CPBA1 SAB1 SBA1
Data I/O
A07 B07
Output Operation Mode
H X H or L H or L X X
Isolation
H X
X X X Input Input Clock An Data into A Register
H X X
XX
Clock Bn Data Into B Register
L H X X L X
An to BnReal Time (Transparent Mode)
LH
X L X Input Output Clock An Data to A Register
L H H or L X H X
LH
XHX
A Register to Bn (Stored Mode)
Clock An Data into A Register and Output to Bn
L L X X X L
Bn to AnReal Time (Transparent Mode)
LLX
X L Output Input Clock Bn Data into B Register
LLX
LLX
H = HIGH Voltage Level
X = Immaterial
L = LOW Voltage Level
= LOW-to-HIGH Transition.
H or L
X
X
H
H
B Register to An (Stored Mode)
Clock Bn into B Register and Output to An
Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control
pins.
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2


Features www.DataSheet4U.com 74LVT16646 • 74LV TH16646 Low Voltage 16-Bit Transceiver/ Register with 3-STATE Outputs January 2000 Revised October 2001 74LVT16646 74LVTH16646 Low Voltage 16-Bit Trans ceiver/Register with 3-STATE Outputs Ge neral Description The LVT16646 and LVTH 16646 contains sixteen noninverting bid irectional registered bus transceivers providing multiplexed transmission of d ata directly from the input bus or from the internal storage registers. Each b yte has separate control inputs which c an be shorted together for full 16-bit operation. The DIR inputs determine the direction of data flow through the dev ice. The CPAB and CPBA inputs load data into the registers on the LOW-to-HIGH transition (see Functional Description) . The LVTH16646 data inputs include bus hold, eliminating the need for external pull-up resistors to hold unused input s. These transceivers are designed for low-voltage (3.3V) VCC applications, bu t with the capability to provide a TTL interface to a 5V environmen.
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