70V27 RAM Datasheet

70V27 Datasheet, PDF, Equivalent


Part Number

70V27

Description

HIGH-SPEED 3.3V STATIC RAM

Manufacture

Integrated Device Technology

Total Page 21 Pages
Datasheet
Download 70V27 Datasheet


70V27
HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
IDT70V27S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features:
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 15/20/35ns (max.)
Low-power operation
– IDT70V27S
Active: 500mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V27L
Active: 500mW (typ.)
Standby: 660μW (typ.)
Separate upper-byte and lower-byte control for bus
matching capability
On-chip port arbitration logic
Dual chip enables allow for depth expansion without
external logic
IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 100-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O8-15L
I/O0-7L
BUSYL (1,2)
I/O
Control
I/O
Control
A14L
A0L
Address
Decoder
A14L
A0L
CE0L
CE1L
OEL
R/WL
32Kx16
MEMORY
ARRAY
70V27
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEM L
NOTES:
INT
(2)
L
M/S (2)
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).
Address
Decoder
A14R
A0R
CE0R
CE1R
OER
R/WR
6.011
©2019 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
I/O8-15R
I/O0-7R
BUSYR(1,2)
,
A14R
A0R
SEMR
INTR(2)
3603 drw 01
JANUARY 2019
DSC 3603/17

70V27
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Description:
The IDT70V27 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit and wider word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
Commercial and Industrial Temperature Range
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE0 andCE1) permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these
devices typically operate on only 500mW of power. The IDT70V27 is
packaged in a 100-pin Thin Quad Flatpack (TQFP).
2


Features HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATI C RAM IDT70V27S/L LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPI RES JUNE 15, 2018 Features: ◆ True D ual-Ported memory cells which allow sim ultaneous access of the same memory loc ation ◆ High-speed access – Commerc ial: 15/20/25/35/55ns (max.) – Indust rial: 15/20/35ns (max.) ◆ Low-power o peration – IDT70V27S Active: 500mW (t yp.) Standby: 3.3mW (typ.) – IDT70V27 L Active: 500mW (typ.) Standby: 660μW (typ.) ◆ Separate upper-byte and lowe r-byte control for bus matching capabil ity ◆ On-chip port arbitration logic ◆ Dual chip enables allow for depth expansion without external logic ◆ ID T70V27 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one de vice ◆ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ Busy and Interrupt Flags ◆ Full on-chip hardware support of semap hore signaling between ports ◆ Fully asynchronous operation from either port ◆ LVTTL-compati.
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