nanoDac. AD5040 Datasheet

AD5040 nanoDac. Datasheet pdf. Equivalent

AD5040 Datasheet
Recommendation AD5040 Datasheet
Part AD5040
Description nanoDac
Feature AD5040; Fully Accurate 14-/16-Bit VOUT nanoDAC™ SPI Interface 2.7 V to 5.5 V, in an SOT-23 AD5040/AD5060 FE.
Manufacture Analog Devices
Datasheet
Download AD5040 Datasheet





Analog Devices AD5040
Fully Accurate 14-/16-Bit VOUT nanoDAC
SPI Interface 2.7 V to 5.5 V, in an SOT-23
AD5040/AD5060
FEATURES
Single 14-/16-bit DAC, 1 LSB INL
Power-on reset to midscale or zero scale
Guaranteed monotonic by design
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
Small 8-lead SOT-23 package, low power
Fast settling time of 4 μs typically
2.7 V to 5.5 V power supply
Low glitch on power-up
SYNC interrupt facility
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5040 and the AD5060, members of the ADI nanoDAC
family, are low power, single 14-/16-bit buffered voltage-out
DACs that operate from a single 2.7 V to 5.5 V supply. The
AD5040/AD5060 parts offer a relative accuracy specification
of ±1 LSB and operation are guaranteed monotonic with a
±1 LSB DNL specification. The parts use a versatile 3-wire serial
interface that operates at clock rates up to 30 MHz and is
compatible with standard SPI®, QSPI™, MICROWIRE™, and
DSP interface standards. The reference for both the AD5040
and AD5060 is supplied from an external VREF pin. A reference
buffer is also provided on-chip. The AD5060 incorporates a
power-on reset circuit that ensures the DAC output powers up
to midscale or zero scale and remains there until a valid write
takes place to the device. The AD5040 and the AD5060 both
contain a power-down feature that reduces the current con-
sumption of the device to typically 330 nA at 5 V and provides
software-selectable output loads while in power-down mode.
The parts are put into power-down mode over the serial
interface. Total unadjusted error for the parts is <2 mV.
Both parts exhibit very low glitch on power-up.
FUNCTIONAL BLOCK DIAGRAM
VREF
VDD
POWER-ON
RESET
BUF
DAC
REGISTER
REF(+)
DAC
OUTPUT
BUFFER
AD5040/
AD5060
VOUT
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
AGND
SYNC SCLK DIN
DACGND
Figure 1.
PRODUCT HIGHLIGHTS
1. Available in a small, 8-lead SOT-23 package.
2. 14-/16-bit accurate, 1 LSB INL.
3. Low glitch on power-up.
4. High speed serial interface with clock speeds up to 30 MHz.
5. Three power-down modes available to the user.
6. Reset to known output voltage (midscale, zero scale).
Table 1. Related Devices
Part No. Description
AD5061 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 4 LSB INL, SOT-23
AD5062 2.7 V to 5.5 V, 16-bit nanoDAC D/A,1 LSB INL, SOT-23
AD5063 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 1 LSB INL, MSOP
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005-2010 Analog Devices, Inc. All rights reserved.



Analog Devices AD5040
AD5040/AD5060
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Product Highlights ........................................................................... 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
Timing Characteristics..................................................................... 5 
Absolute Maximum Ratings............................................................ 6 
ESD Caution.................................................................................. 6 
Pin Configuration and Function Descriptions............................. 7 
Typical Performance Characteristics ............................................. 8 
Terminology .................................................................................... 14 
Theory of Operation ...................................................................... 15 
DAC Architecture....................................................................... 15 
REVISION HISTORY
1/10—Rev. 0 to Rev. A
Changes to Table 2, Relative Accuracy (INL) and Endnote 1 .... 3
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
10/05—Revision 0: Initial Version
Reference Buffer ......................................................................... 15 
Serial Interface ............................................................................ 15 
Power-On reset ........................................................................... 16 
Software Reset............................................................................. 16 
Power-Down Modes .................................................................. 17 
Microprocessor Interfacing....................................................... 17 
Applications..................................................................................... 19 
Choosing a Reference for the AD5040/ AD5060................... 19 
Bipolar Operation Using the AD5040/ AD5060.................... 19 
Using the AD5040/AD5060 with a Galvanically Isolated
Interface Chip ............................................................................. 20 
Power Supply Bypassing and Grounding................................ 20 
Outline Dimensions ....................................................................... 21 
Ordering Guide .......................................................................... 21 
Rev. A | Page 2 of 24



Analog Devices AD5040
AD5040/AD5060
SPECIFICATIONS
VDD = 5.5 V, VREF = 4.096 V @ RL = unloaded, CL = unloaded; TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy (INL)2
Total Unadjusted Error (TUE)2
Differential Nonlinearity (DNL)2
A, B, and Y Grades1
Min Typ
Max
16
14
±0.5
±0.5
±0.5
±0.1
±0.1
±0.5
±2
±1
±1.5
±2.0
±2.0
±1
±0.5 ±1
Gain Error
Gain Error Temperature Coefficient
Offset Error
Offset Error Temperature Coefficient
Full-Scale Error
±0.01
±0.01
1
±0.02
±0.02
0.5
±0.05
±0.02
±0.03
±1.5
±2.0
±2.0
±0.05
±2.0
OUTPUT CHARACTERISTICS3
Output Voltage Range
Output Voltage Settling Time
0
4
VREF
Output Noise Spectral Density
Output Voltage Noise
64
6
Digital-to-Analog Glitch Impulse
2
Digital Feedthrough
DC Output Impedance (Normal)
DC Output Impedance (Power-Down)
(Output Connected to 1 kΩ Network)4
(Output Connected to 100 kΩ
Network)
Capacitive Load Stability
Slew Rate
0. 003
0. 015
1
100
1. 2
1
Short-Circuit Current
60
45
DAC Power-Up Time
4.5
DC Power Supply Rejection Ratio
−92.11
Unit Test Conditions/Comments
Bits
Bits
LSB
LSB
mV
LSB
% of FSR
ppm of FSR/°C
mV
μV/°C
mV
AD5060
AD5040
−40°C to +85°C, AD5040/AD5060 A grade
−40°C to +85°C, AD5040/AD5060 B grade
−40°C to +125°C, AD5060 Y grade
−40°C to +85°C, AD5040/AD5060
−40°C to +125°C, AD5060 Y grade
Guaranteed monotonic,
−40°C to +85°C, AD5040/AD5060
Guaranteed monotonic,
−40°C to +125°C, Y grade
TA = −40°C to +85°C, AD5040/AD5060
TA = −40°C to +125°C AD5060 Y grade
TA = −40°C to + 85°C, AD5040/AD5060
TA = −40°C to + 125°C, AD5060 Y grade
All 1s loaded to DAC register,
AD5040 AD5060; TA = −40°C to +85°C
All 1s loaded to DAC register,
TA = −40°C to +125°C, AD5060 Y grade
V
μs
nV/Hz
μV p-p
nV-s
nV-s
Ω
¼ scale to ¾ scale code transition to
±1 LSB, RL = 5 kΩ
DAC code = midscale, 1 kHz
DAC code = midscale , 0.1 Hz to 10 Hz
bandwidth
1 LSB change around code 57386,
RL = 5 kΩ, CL = 200 pF
DAC code = full scale
Output impedance tolerance ±10%
kΩ Output impedance tolerance ±400 Ω
kΩ Output impedance tolerance ±20 kΩ
nF Loads used RL = 5 kΩ, RL = 100 kΩ, RL = ∞
V/μs ¼ scale to ¾ scale code transition to
±1 LSB, RL = 5 kΩ, CL = 200 pF
ma DAC code = full scale, output shorted to
GND, TA = 25°C
DAC code = zero scale, output shorted to
VDD, TA = 25°C
μs Time to exit power-down mode to normal
mode of AD5060, 24th clock edge to 90%
of DAC final value, output unloaded
db VDD ± 10%, DAC code = full scale
Rev. A | Page 3 of 24





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