AND gate. 74AHCT2G08 Datasheet

74AHCT2G08 gate. Datasheet pdf. Equivalent


Part 74AHCT2G08
Description Dual 2-input AND gate
Feature 74AHC2G08; 74AHCT2G08 Dual 2-input AND gate Rev. 5 — 27 November 2013 Product data sheet 1. Gener.
Manufacture NXP Semiconductors
Datasheet
Download 74AHCT2G08 Datasheet


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74AHCT2G08
74AHC2G08; 74AHCT2G08
Dual 2-input AND gate
Rev. 5 — 27 November 2013
Product data sheet
1. General description
The 74AHC2G08; 74AHCT2G08 is a high-speed Si-gate CMOS device.
The 74AHC2G08; 74AHCT2G08 provides two 2-input AND gates.
2. Features and benefits
Symmetrical output impedance
High noise immunity
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Low power dissipation
Balanced propagation delays
Multiple package options
Specified from 40 C to +80 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AHC2G08DP 40 C to +125 C TSSOP8
74AHCT2G08DP
74AHC2G08DC 40 C to +125 C VSSOP8
74AHCT2G08DC
74AHC2G08GD 40 C to +125 C XSON8
74AHCT2G08GD
Description
Version
plastic thin shrink small outline package; 8 leads; body SOT505-2
width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3 2 0.5 mm



74AHCT2G08
NXP Semiconductors
74AHC2G08; 74AHCT2G08
Dual 2-input AND gate
4. Marking
Table 2. Marking
Type number
74AHC2G08DP
74AHCT2G08DP
74AHC2G08DC
74AHCT2G08DC
74AHC2G08GD
74AHCT2G08GD
Marking code[1]
A08
C08
A08
C08
A08
C08
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1 1A
2 1B
5 2A
6 2B
Fig 1. Logic symbol.
1Y 7
2Y 3
mna724
1 &7
2
5 &3
6
mna725
Fig 2. IEC logic symbol.
A
B
Fig 3. Logic diagram (one gate).
Y
mna221
74AHC_AHCT2G08
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
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