AD7280 System Datasheet

AD7280 Datasheet PDF, Equivalent


Part Number

AD7280

Description

Lithium Ion Battery Monitoring System

Manufacture

Analog Devices

Total Page 30 Pages
PDF Download
Download AD7280 Datasheet PDF


AD7280
Preliminary Technical Data
FEATURES
12-bit ADC, 1us per channel conversion time
6 Analog Input Channels, CM range 0.5V to 27.5V
6 Temperature Measurements Inputs.
On Chip Voltage Regulator
Cell Balancing Interface
Daisy Chain Interface
www.DataShee3t4pUp.cmomReference
Low Quiescent Current
High Input Impedance
Serial Interface with Alert Function
1 SPI interface for up to 300 channels
On Chip Registers for Channel Sequencing
VDD Operating Range 7.5V to 30V
Temperature Range -40 oC to 105oC
48 lead LQFP and LFCSP Packages
APPLICATIONS
Lithium Ion Battery Monitoring
Nickel Metal Hydride Battery Monitoring
GENERAL DESCRIPTION
The AD72801 contains all the functions required for general
purpose monitoring of stacked Lithium Ion batteries as used in
Hybrid Electric Vehicles. The part has multiplexed analog input
and temperature measurement channels for up to six cells of
battery management. An internal 3-ppm reference is provided
to drive the ADC. The ADC resolution is 12 bits with a 1 Msps
throughput rate offering a 1µs conversion time.
The AD7280 operates from just one VDD supply which has a
range of 7.5V to 30V (with an absolute max rating of 33V). The
part provides 6 pseudo differential analog input channels to
accommodate large common mode signals across the full VDD
range. Each channel allows an input signal range, Vin(+) --
Vin(-), of 0V to 5V. The input pins assume a series stack of 6
cells. In addition the part can accommodate 6 external sensors
for temperature measurement.
The AD7280 includes on chip registers which allow a sequence
of channel measurements to be programmed to suit the
applications requirements.
Lithium Ion Battery
Monitoring System
AD7280
FUNCTIONAL BLOCK DIAGRAM
VDD
Vin(6)
Vin(5)
Vin(4)
Vin(3)
Vin(2)
Vin(1)
Vin(0)
AD7280
MUX
VT(6)
VT(5)
VT(4)
VT(3)
VT(2)
VT(1)
VT TERM
VREF
CREF
REFGND
DAIS Y CHAIN
INTER FACE
++
--
CLOCK
2.5V
REF
CB1
CB6
CEL L
BALANCING
INTER FACE
REGUL ATOR
12 BIT ADC
CONTRO L LOGIC
& SELF TEST
LIMIT REG
SQN LOGIC
DATA MEMO RY
SPI INTER FACE
VREG
DGND
DVCC
AVCC
VDRIVE
SCLK
S D IN
SDOUT
ALERT
CS
PD
CNVST
MASTER
Figure 1
The AD7280 also includes an Alert function which generates an
interrupt output signal if the cell voltages exceed an upper or
lower limit defined by the user. The AD7280 has balancing
interface outputs designed to control external FET transistors to
allow discharging of individual cells.
The AD7280 includes a Built In Self Test feature which
internally applies a known voltage to the ADC inputs.
There is a daisy chain interface which allows up to 50 parts to
be stacked without the need for individual device isolation.
The AD7280 requires only one supply pin which takes 7mA
under normal operation, while converting at 1 Msps.
All this functionality is provided in a 48 pin LQFP or 48 pin
LFCSP package operating over a temperature range of −40°C to
+105°C.
1 Patents Pending
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.

AD7280
AD7280
Preliminary Technical Data
SPECIFICATIONS
VDD = 7.5 V to 30 V, VSS = 0 V, DVCC = AVCC = VREG, VDRIVE = 2.7 V to 5.25 V, TA = -40oC to 105oC, unless otherwise noted
Table 1.
Parameter1
Min
Typ Max Unit
Test Conditions/Comments
DC ACCURACY [Vin(0) to Vin(6)]2
Resolution
12
Bits No Missing Codes
Integral Nonlinearity
±1 LSB
Differential Nonlinearity
±1 LSB
Offset Error
1 LSB
Offset Error Drift
3 ppm/oC
Offset Error Match
1 LSB
w w wGain.ErroDr a t a S h e e 1 t 4 U . c LSBo m
Gain Error Drift
2 ppm/oC
Gain Error Match
1 LSB
ADC Unadjusted Error3
0.05 0.1
%
-40oC to 85oC
0.08 0.3
%
-40oC to 105oC
Total Unadjusted Error4
0.07 0.2
%
-40oC to 85oC
0.1 0.5 %
-40oC to 105oC
ANALOG INPUTS [Vin(0) to
Vin(6)]
Pseudo Differential Input
Voltage
Vin(n) – Vin(n-1)
Absolute Input Voltage
1V
VCM - VREF
Common Mode Input Voltage 0.5
2VREF
VCM +
VREF
27.5
V
V
V
DC Leakage Current
±70 nA CNVST pulse every 100ms
Input Capacitance
15 pF When in track
3 pF When in hold
DC ACCURACY [VT1 to VT6]2
Resolution
12
Bits No Missing Codes
Integral Nonlinearity
±1 LSB
Differential Nonlinearity
±1 LSB
Offset Error
2 LSB
Offset Error Drift
2 ppm/oC
Offset Error Match
2 LSB
Gain Error
2 LSB
Gain Error Drift
1.2 ppm/oC
Gain Error Match
2 LSB
ADC Unadjusted Error5
0.1 0.2 %
-40oC to 85oC
0.16 0.6
%
-40oC to 105oC
Total Unadjusted Error6
0.15 0.4
%
-40oC to 85oC
0.2 1
%
-40oC to 105oC
ANALOG INPUTS (VT1 to VT6)
Input Voltage Range
0
2VREF
V
Leakage Current
±70 nA CNVST pulse every 100ms
Input Capacitance
15 pF When in track
3 pF When in hold
DYNAMIC PERFORMANCE
Common Mode Rejection Ratio
[CMRR]
-75
dB Up to 10kHz ripple frequency
Rev. PrD | Page 2 of 33


Features Preliminary Technical Data FEATURES 12-b it ADC, 1us per channel conversion time 6 Analog Input Channels, CM range 0.5V to 27.5V 6 Temperature Measurements In puts. On Chip Voltage Regulator Cell Ba lancing Interface Daisy Chain Interface www.DataSheet4U.com 3 ppm Reference Lo w Quiescent Current High Input Impedanc e Serial Interface with Alert Function 1 SPI interface for up to 300 channels On Chip Registers for Channel Sequencin g VDD Operating Range 7.5V to 30V Tempe rature Range -40 oC to 105oC 48 lead LQ FP and LFCSP Packages Lithium Ion Batt ery Monitoring System AD7280 FUNCTIONAL BLOCK DIAGRAM V DD SCLKhi SDINhi SDOUT hi ALERThi CShi PDhi CNVSThi CB1 CB6 A D7280 Vin(6) Vin(5) Vin(4) Vin(3) Vin(2 ) Vin(1) Vin(0) MUX + - DAIS Y CHAIN I NTER FACE CEL L BALANCING INTER FACE R EGUL ATOR VREG DGND DVCC + - 12 BIT ADC AVCC VDRIVE VT(6) VT(5) VT(4) VT( 3) VT(2) VT(1) VT TERM CLOCK CONTRO L LOGIC & SELF TEST SCLK SDIN SDO UT ALE RT CS PD CNVST MASTER VREF CREF REFGND 2.5V REF LIMIT REG SQ.
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