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dual buffer. 74AUP2G07 Datasheet

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dual buffer. 74AUP2G07 Datasheet






74AUP2G07 buffer. Datasheet pdf. Equivalent




74AUP2G07 buffer. Datasheet pdf. Equivalent





Part

74AUP2G07

Description

Low-power dual buffer



Feature


www.DataSheet4U.com 74AUP2G07 Low-power dual buffer with open-drain output Rev . 02 — 12 June 2007 Product data shee t 1. General description The 74AUP2G07 provides two non-inverting buffers wit h open-drain output. The output of the device is an open drain and can be conn ected to other open-drain outputs to im plement active-LOW wired-OR or active-H IGH wired-AND functi.
Manufacture

NXP Semiconductors

Datasheet
Download 74AUP2G07 Datasheet


NXP Semiconductors 74AUP2G07

74AUP2G07; ons. Schmitt-trigger action at all input s makes the circuit tolerant to slower input rise and fall times across the en tire VCC range from 0.8 V to 3.6 V. Thi s device ensures a very low static and dynamic power consumption across the en tire VCC range from 0.8 V to 3.6 V. Thi s device is fully specified for partia l power-down applications using IOFF. T he IOFF circuitry di.


NXP Semiconductors 74AUP2G07

sables the output, preventing the damagi ng backflow current through the device when it is powered down. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Compli es with JEDEC standards: x JESD8-12 (0. 8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8 -5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protec.


NXP Semiconductors 74AUP2G07

tion: x HBM JESD22-A114E Class 3A exceed s 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101C exceeds 1000 V s Low static-power consumption; ICC = 0.9 µA (maximum) s Latch-up performance e xceeds 100 mA per JESD 78 Class II s In puts accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % o f VCC s IOFF circuitry provides partial Power-down mode op.

Part

74AUP2G07

Description

Low-power dual buffer



Feature


www.DataSheet4U.com 74AUP2G07 Low-power dual buffer with open-drain output Rev . 02 — 12 June 2007 Product data shee t 1. General description The 74AUP2G07 provides two non-inverting buffers wit h open-drain output. The output of the device is an open drain and can be conn ected to other open-drain outputs to im plement active-LOW wired-OR or active-H IGH wired-AND functi.
Manufacture

NXP Semiconductors

Datasheet
Download 74AUP2G07 Datasheet




 74AUP2G07
www.DataSheet4U.com
74AUP2G07
Low-power dual buffer with open-drain output
Rev. 02 — 12 June 2007
Product data sheet
1. General description
The 74AUP2G07 provides two non-inverting buffers with open-drain output. The output of
the device is an open drain and can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114E Class 3A exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101C exceeds 1000 V
s Low static-power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from 40 °C to +85 °C and 40 °C to +125 °C




 74AUP2G07
www.DNatXaSPheSete4Um.coicmonductors
74AUP2G07
Low-power dual buffer with open-drain output
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP2G07GW 40 °C to +125 °C SC-88
74AUP2G07GM 40 °C to +125 °C XSON6
74AUP2G07GF 40 °C to +125 °C XSON6
Description
Version
plastic surface-mounted package; 6 leads
SOT363
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2. Marking
Type number
74AUP2G07GW
74AUP2G07GM
74AUP2G07GF
5. Functional diagram
Marking code
p7
p7
p7
1 1A
1Y 6
3 2A
2Y 4
mnb092
Fig 1. Logic symbol
1A 1
6 1Y
2A 3
4 2Y
mnb093
Fig 2. IEC logic symbol
Y
A
GND
mna625
Fig 3. Logic diagram (one gate)
74AUP2G07_2
Product data sheet
Rev. 02 — 12 June 2007
© NXP B.V. 2007. All rights reserved.
2 of 16




 74AUP2G07
74AUP2G07w NXwP Semw icon.ductoDrs a t a S h e e t 4 U . c o m
Low-power dual buffer with open-drain output
6. Pinning information
6.1 Pinning
74AUP2G07
74AUP2G07
1A 1
6 1Y
1A 1
GND 2
2A 3
6 1Y
5 VCC
4 2Y
001aad706
GND 2
5 VCC
2A 3
4 2Y
001aad707
Transparent top view
Fig 4. Pin configuration SOT363-1 Fig 5. Pin configuration SOT886
(SC-88)
(XSON6)
6.2 Pin description
Table 3.
Symbol
1A
GND
2A
2Y
VCC
1Y
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data output
7. Functional description
Table 4.
Input
nA
L
H
Function table[1]
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF state.
Output
nY
L
Z
74AUP2G07
1A 1
6 1Y
GND 2
5 VCC
2A 3
4 2Y
001aad665
Transparent top view
Fig 6. Pin configuration SOT891
(XSON6)
74AUP2G07_2
Product data sheet
Rev. 02 — 12 June 2007
© NXP B.V. 2007. All rights reserved.
3 of 16



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