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Wideband Synthesizer. ADF4350 Datasheet

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Wideband Synthesizer. ADF4350 Datasheet
















ADF4350 Synthesizer. Datasheet pdf. Equivalent













Part

ADF4350

Description

Wideband Synthesizer



Feature


Data Sheet Wideband Synthesizer with In tegrated VCO ADF4350 FEATURES GENERAL DESCRIPTION Output frequency range: 1 37.5 MHz to 4400 MHz The ADF4350 allow s implementation of fractional-N or Fr actional-N synthesizer and integer-N sy nthesizer integer-N phase-locked loop (PLL) frequency synthesizers Low phase noise VCO if used with an external lo op filter and exte.
Manufacture

Analog Devices

Datasheet
Download ADF4350 Datasheet


Analog Devices ADF4350

ADF4350; rnal reference Programmable divide-by-1 /-2/-4/-8/-16 output frequency. Typic al rms jitter: <0.4 ps rms Power supply : 3.0 V to 3.6 V Logic compatibility: 1 .8 V Programmable dual-modulus prescale r of 4/5 or 8/9 Programmable output pow er level RF output mute function 3-wire serial interface Analog and digital lo ck detect Switched bandwidth fast-lock mode Cycle slip re.


Analog Devices ADF4350

duction APPLICATIONS The ADF4350 has an integrated voltage controlled oscillat or (VCO) with a fundamental output freq uency ranging from 2200 MHz to 4400 MHz . In addition, divide-by-1/2/4/8 or 16 circuits allow the user to generate RF output frequencies as low as 137.5 MHz. For applications that require isolatio n, the RF output stage can be muted. Th e mute function is.


Analog Devices ADF4350

both pin- and software-controllable. An auxiliary RF output is also available, which can be powered down if not in us e. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. Wireles s infrastructure (W-CDMA, TD-SCDMA, WiM AX, GSM, PCS, DCS.





Part

ADF4350

Description

Wideband Synthesizer



Feature


Data Sheet Wideband Synthesizer with In tegrated VCO ADF4350 FEATURES GENERAL DESCRIPTION Output frequency range: 1 37.5 MHz to 4400 MHz The ADF4350 allow s implementation of fractional-N or Fr actional-N synthesizer and integer-N sy nthesizer integer-N phase-locked loop (PLL) frequency synthesizers Low phase noise VCO if used with an external lo op filter and exte.
Manufacture

Analog Devices

Datasheet
Download ADF4350 Datasheet




 ADF4350
Data Sheet
Wideband Synthesizer with Integrated VCO
ADF4350
FEATURES
GENERAL DESCRIPTION
Output frequency range: 137.5 MHz to 4400 MHz
The ADF4350 allows implementation of fractional-N or
Fractional-N synthesizer and integer-N synthesizer
integer-N phase-locked loop (PLL) frequency synthesizers
Low phase noise VCO
if used with an external loop filter and external reference
Programmable divide-by-1/-2/-4/-8/-16 output
frequency.
Typical rms jitter: <0.4 ps rms
Power supply: 3.0 V to 3.6 V
Logic compatibility: 1.8 V
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast-lock mode
Cycle slip reduction
APPLICATIONS
The ADF4350 has an integrated voltage controlled oscillator
(VCO) with a fundamental output frequency ranging from
2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16
circuits allow the user to generate RF output frequencies as low
as 137.5 MHz. For applications that require isolation, the RF
output stage can be muted. The mute function is both pin- and
software-controllable. An auxiliary RF output is also available,
which can be powered down if not in use.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,
GSM, PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation
FUNCTIONAL BLOCK DIAGRAM
SDVDD
AVDD
DVDD
VP RSET VVCO
REFIN
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER FRACTION MODULUS
REG
REG
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
VCO
CORE
FLO SWITCH
÷1/2/4/8/16
OUTPUT
STAGE
OUTPUT
STAGE
MUXOUT
SW
LD
CPOUT
VTUNE
VREF
VCOM
TEMP
RFOUTA+
RFOUTA–
PDBRF
RFOUTB+
RFOUTB–
CE AGND
DGND
CPGND
Figure 1.
MULTIPLEXER
SDGND AGNDVCO
ADF4350
Rev. B
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 ADF4350
ADF4350* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• ADF4350 Evaluation Board
Documentation
Application Notes
• AN-0974: Multicarrier TD-SCMA Feasibility
Data Sheet
• ADF4350: Wideband Synthesizer with Integrated VCO
Data Sheet
User Guides
• UG-109: Evaluation Board User Guide for ADF4350
• UG-110: Evaluation User Guide for ADF4350
• UG-476: PLL Software Installation Guide
Software and Systems Requirements
• ADF4350 IIO Wideband Synthesizer Linux Driver
• AD9739A Native FMC Card / Xilinx Reference Designs
Tools and Simulations
• ADIsimPLL™
• ADIsimRF
• ADF4350 IBIS Model
Reference Designs
• CN0134
• CN0144
• CN0147
• CN0232
• CN0245
Reference Materials
Press
• Analog Devices’ 4-GHz PLL Synthesizer Offers Leading
Phase Noise Performance
• New Analog Devices’ PLL Synthesizers Deliver Utmost
Flexibility and Phase Noise Performance
Product Selection Guide
• RF Source Booklet
Technical Articles
• Direct Conversion Receiver Designs Enable Multi-standard/
Multi-band Operation
• Get the Best from Your Low-Dropout Regulator
Design Resources
• ADF4350 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
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Technical Support
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 ADF4350
ADF4350
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
Timing Characteristics ................................................................ 5 
Absolute Maximum Ratings............................................................ 6 
Transistor Count........................................................................... 6 
ESD Caution.................................................................................. 6 
Pin Configuration and Function Descriptions............................. 7 
Typical Performance Characteristics ............................................. 9 
Circuit Description......................................................................... 11 
Reference Input Section............................................................. 11 
RF N Divider ............................................................................... 11 
INT, FRAC, MOD, and R Counter Relationship.................... 11 
INT N MODE ............................................................................. 11 
R Counter .................................................................................... 11 
Phase Frequency Detector (PFD) and Charge Pump............ 11 
MUXOUT and LOCK Detect................................................... 12 
Input Shift Registers ................................................................... 12 
Program Modes .......................................................................... 12 
VCO.............................................................................................. 12 
Output Stage................................................................................ 13 
Register Maps .................................................................................. 14 
Register 0 ..................................................................................... 18 
REVISION HISTORY
5/16—Rev. A to Rev. B
Changes to Figure 3.......................................................................... 7
Changes to the ADuC7019 to ADuC7029 Family Interface
Section, Figure 35, and Figure 35 Caption .................................. 26
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 30
Register 1 ..................................................................................... 18 
Register 2 ..................................................................................... 18 
Register 3 ..................................................................................... 20 
Register 4 ..................................................................................... 20 
Register 5 ..................................................................................... 20 
Initialization Sequence .............................................................. 21 
RF Synthesizer—A Worked Example ...................................... 21 
Modulus....................................................................................... 21 
Reference Doubler and Reference Divider ............................. 21 
12-Bit Programmable Modulus................................................ 21 
Cycle Slip Reduction for Faster Lock Times........................... 22 
Spurious Optimization and Fast lock ...................................... 22 
Fast-Lock Timer and Register Sequences ............................... 22 
Fast Lock—An Example ............................................................ 22 
Fast Lock—Loop Filter Topology............................................. 23 
Spur Mechanisms ....................................................................... 23 
Spur Consistency and Fractional Spur Optimization ........... 24 
Phase Resync............................................................................... 24 
Applications Information .............................................................. 25 
Direct Conversion Modulator .................................................. 25 
Interfacing ................................................................................... 26 
PCB Design Guidelines for a Chip Scale Package ................. 26 
Output Matching ........................................................................ 27 
Outline Dimensions ....................................................................... 31 
Ordering Guide .......................................................................... 31 
4/11—Rev. 0 to Rev. A
Changes to Typical rms Jitter in Features Section.........................1
Changes to Specifications.................................................................3
Changes Output Stage Section...................................................... 13
Changes to Figure 29...................................................................... 17
Changes to Fast Lock—An Example Section ............................. 22
Changes to Direct Conversion Modulator Section and
Figure 34 ......................................................................................... 25
Changes to ADuC70xx Interface Section and ADSP-BF527
Interface Section ............................................................................. 26
Changes to Output Matching Section and Table 7 .................... 27
Added Table 8 ................................................................................. 28
Changes to Ordering Guide .......................................................... 29
11/08—Revision 0: Initial Version
Rev. B | Page 2 of 34




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