(CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM
Description
CY7C1370B CY7C1372B
512K × 36/1M × 18 Pipelined SRAM with NoBL Architecture
Features
Zero Bus Latency, no dead cycles between Write and Read cycles Fast clock speed: 200, 167, 150, and 133 MHz Fast access time: 3.0, 3.4, 3.8, and 4.2 ns Internally synchronized registered outputs eliminate the need to control OE Single 3.3V –5% and +10% power supp...
