SRAM. IC61S25636T Datasheet

IC61S25636T Datasheet PDF


Part

IC61S25636T

Description

8Mb SyncBurst Pipelined SRAM

Manufacture

Integrated Circuit Solution

Page 22 Pages
Datasheet
Download IC61S25636T Datasheet


IC61S25636T Datasheet
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
Document Title
8Mb SyncBurst Pipelined SRAM
Revision History
Revision No
0A
0B
History
Draft Date
Remark
Initial Draft
1. Move the FT pin for user-configurable Flow
throught or pipelineed operation, That pin can be
NC or connected to VCC for pipelined operation.
Refer to Pin configuration.
2. Revise the power supply charaetoristics at page 12
3. Resive the tKQ of 250 MHZ from 2.5ns to 3ns.
4. Move the 100 MHZ speed grade.
September 24,2001
August 13,2002
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
1
Free Datasheet http://www.datasheet4u.com/

IC61S25636T Datasheet
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
256K x 32, 256K x 36, 512K x 18
8Mb S/DCD SYNCBURST Pipelined SRAMs
FEATURES
• Pipeline Mode operation
• Single/Dual Cycl Deselect
• User-selectable Output Drive Strength with XQ Mode
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Pentium™ or linear burst sequence control using
MODE input
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and 119-pin PBGA package
• Single +3.3V, +10%, –5% core power supply
• Power-down snooze mode
• 2.5V or 3.3V I/O Supply
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• D version (two chip selects)
DESCRIPTION
ICSI's 8Mb SyncBurst Pipelined SRAMs integrate a 512k
x 18, 256k x 32, or 256k x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
Applications
The ICSI SyncBurst Pipelined SRAM family employs
high-speed ,low-power CMOS designs that are fabricated
using an advanced CMOS process to provide Level 2
Cache applications supporting Pentium and PowerPC
microprocessors originally, the device now finds applica-
tion ranging from DSP main store to networking chip set
support.
FAST ACCESS TIME
Symbol
-250 -200 -166 -133 Units
Pipeline tKQ
3 3.1 3.5 4 ns
3-1-1-1 tKC
4 5 6 7.5 ns
ICC1 390 360 330 300 mA
Controls
All synchronous inputs pass through registers controlled by a
positive-edge-triggered single clock input.Bursts can be initiated
with either ADSP (Address Status Processor) or ADSC (Address
Status Cache Controller) input pins. Subsequent burst ad-
dresses can be generated internally and controlled by the ADV
(burst address advance) input pin. The mode pin is used to select
the burst sequence order, Linear burst is achieved when this pin
is tied LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating.
SCD and DCD Pipelined Reads
The device is a SCD (Single Cycle Deselect) and DCD(Dual
Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs
pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input on Bump 4L.
Byte Write and Global Write
Write cycles are internally self-timed and are initiated by the rising
edge of the clock input. Write cycles can be from one to four bytes
wide as controlled by the write control inputs.Separate byte
enables allow individual bytes to be written. Byte write operation
is performed by using byte write enable (BWE).input combined
with one or more individualbyte write signals (BWx). In addition,
Global Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
IOL/IOH Drive strength Options
The XQ pin allows selection between high drive strength (XQ
low) for multi-drop bus applications and normal drive strength
(XQ floating or high) point-to-point applications. See the Output
Driver Characteristics chart for details.
Snooze Mode
Low power (Snooze mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK). Memory
data is retained during Snooze mode.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
Free Datasheet http://www.datasheet4u.com/


Features Datasheet pdf IC61S25632T/D IC61S25636T/D IC61S51218T/ D Document Title 8Mb SyncBurst Pipelin ed SRAM Revision History Revision No 0A 0B History Initial Draft 1. Move the FT pin for user-configurable Flow throu ght or pipelineed operation, That pin c an be NC or connected to VCC for pipeli ned operation. Refer to Pin configurati on. 2. Revise the power supply charaeto ristics at page 12 3. Resive the tKQ of 250 MHZ from 2.5ns to 3ns. 4. Move the 100 MHZ speed grade. Draft Date Rema rk September 24,2001 August 13,2002 T he attached datasheets are provided by ICSI. Integrated Circuit Solution Inc r eserve the right to change the specific ations and products. ICSI will answer t o your questions about device. If you h ave any questions, please contact the I CSI offices. Integrated Circuit Soluti on Inc. SSR014-0B 08/13/2002 1 Free Da tasheet http://www.datasheet4u.com/ IC 61S25632T/D IC61S25636T/D IC61S51218T/D 256K x 32, 256K x 36, 512K x 18 8Mb S /DCD SYNCBURST Pipelined SRAMs FEATURES • • • • • • • • • • • •.
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