36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs
Description
36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs
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ISSI
May 2005
®
Features
1M x 36 or 2M x 18. On-chip delay-locked loop (DLL) for wide data valid window. Separate read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double data rate (DDR) interface for read and write ...
