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FQP33N10. 33N10 Datasheet

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FQP33N10. 33N10 Datasheet






33N10 FQP33N10. Datasheet pdf. Equivalent




33N10 FQP33N10. Datasheet pdf. Equivalent





Part

33N10

Description

FQP33N10



Feature


FQP33N10 April 2000 QFET FQP33N10 100V N-Channel MOSFET General Description T hese N-Channel enhancement mode power f ield effect transistors are produced us ing Fairchild’s proprietary, planar s tripe, DMOS technology. This advanced t echnology has been especially tailored to minimize on-state resistance, provid e superior switching performance, and w ithstand high energy.
Manufacture

Fairchild Semiconductor

Datasheet
Download 33N10 Datasheet


Fairchild Semiconductor 33N10

33N10; pulse in the avalanche and commutation mode. These devices are well suited for low voltage applications such as audio amplifier, high efficiency switching D C/DC converters, and DC motor control. TM Features • • • • • • 33A, 100V, RDS(on) = 0.052Ω @VGS = 10 V Low gate charge ( typical 38 nC) Low Crss ( typical 62 pF) Fast switchin g 100% avalanche tested Improved d.


Fairchild Semiconductor 33N10

v/dt capability 175°C maximum junction temperature rating D ! " G G! DS ! " " " TO-220 FQP Series ! S Absolute Maximum Ratings Symbol VDSS ID IDM V GSS EAS IAR EAR dv/dt PD TJ, TSTG TL T C = 25°C unless otherwise noted Param eter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed ( Note 1) FQP33N10 100 .


Fairchild Semiconductor 33N10

33 23 132 ±25 (Note 2) (Note 1) (Note 1) (Note 3) Units V A A A V mJ A mJ V/ ns W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanc he Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipa tion (TC = 25°C) 435 33 12.7 6.0 127 0.85 -55 to +175 300 - Derate above 25 °C Operating and Storage Temperature R ange Maximum lead temper.

Part

33N10

Description

FQP33N10



Feature


FQP33N10 April 2000 QFET FQP33N10 100V N-Channel MOSFET General Description T hese N-Channel enhancement mode power f ield effect transistors are produced us ing Fairchild’s proprietary, planar s tripe, DMOS technology. This advanced t echnology has been especially tailored to minimize on-state resistance, provid e superior switching performance, and w ithstand high energy.
Manufacture

Fairchild Semiconductor

Datasheet
Download 33N10 Datasheet




 33N10
FQP33N10
100V N-Channel MOSFET
April 2000
QFETTM
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as audio amplifier,
high efficiency switching DC/DC converters, and DC motor
control.
Features
• 33A, 100V, RDS(on) = 0.052@VGS = 10 V
• Low gate charge ( typical 38 nC)
• Low Crss ( typical 62 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• 175°C maximum junction temperature rating
GD S
TO-220
FQP Series
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
Parameter
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Drain-Source Voltage
Drain Current
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
- Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8 from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
RθCS
RθJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case-to-Sink
Thermal Resistance, Junction-to-Ambient
D
!
"
!"
G!
"
"
!
S
FQP33N10
100
33
23
132
±25
435
33
12.7
6.0
127
0.85
-55 to +175
300
Typ Max
-- 1.18
0.5 --
-- 62.5
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Units
°CW
°CW
°CW
©2000 Fairchild Semiconductor International
Rev. A, April 2000




 33N10
Electrical CharacteristicsTC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
BVDSS
/ TJ
IDSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
IGSSF
IGSSR
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
VGS = 0 V, ID = 250 µA
ID = 250 µA, Referenced to 25°C
VDS = 100 V, VGS = 0 V
VDS = 80 V, TC = 150°C
VGS = 25 V, VDS = 0 V
VGS = -25 V, VDS = 0 V
100
--
--
--
--
--
--
0.11
--
--
--
--
--
--
1
10
100
-100
V
V/°C
µA
µA
nA
nA
On Characteristics
VGS(th)
RDS(on)
Gate Threshold Voltage
Static Drain-Source
On-Resistance
gFS Forward Transconductance
VDS = VGS, ID = 250 µA
VGS = 10 V, ID = 16.5 A
VDS = 40 V, ID = 16.5 A (Note 4)
2.0 --
4.0
-- 0.040 0.052
-- 22
--
V
S
Dynamic Characteristics
Ciss
Coss
Input Capacitance
Output Capacitance
Crss Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
-- 1150 1500
-- 320 420
-- 62 80
pF
pF
pF
Switching Characteristics
td(on)
tr
td(off)
tf
Qg
Qgs
Qgd
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 50 V, ID = 33 A,
RG = 25
-- 15 40
-- 195 400
-- 80 170
(Note 4, 5)
--
110
230
VDS = 80 V, ID = 33 A,
-- 38 51
VGS = 10 V
-- 7.5
--
(Note 4, 5) --
18
--
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain-Source Diode Forward Current
-- --
33
ISM Maximum Pulsed Drain-Source Diode Forward Current
-- -- 132
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 33 A
-- -- 1.5
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
VGS = 0 V, IS = 33 A,
dIF / dt = 100 A/µs
-- 80
(Note 4) -- 0.22
--
--
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.6mH, IAS = 33A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C
3. ISD  33A, di/dt  300A/µs, VDD  BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width  300µs, Duty cycle  2%
5. Essentially independent of operating temperature
A
A
V
ns
µC
©2000 Fairchild Semiconductor International
Rev. A, April 2000




 33N10
Typical Characteristics
102 Top :
VGS
15.0 V
10.0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom: 4.5 V
101
100
10-1
Notes :
1. 250s Pulse Test
2. TC = 25
100
V , Drain-Source Voltage [V]
DS
101
Figure 1. On-Region Characteristics
0.20
0.15
0.10
V = 10V
GS
V = 20V
GS
0.05
0.00
0
 Note : T = 25
J
20 40 60 80 100 120
ID, Drain Current [A]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
3000
2500
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
2000
1500
Ciss
Coss
Notes :
1. VGS = 0 V
2. f = 1 MHz
1000
500
Crss
0
10-1 100 101
V , Drain-Source Voltage [V]
DS
Figure 5. Capacitance Characteristics
102
101
175
25
-55
Notes :
1. VDS = 40V
2. 250s Pulse Test
100
2 4 6 8 10
V , Gate-Source Voltage [V]
GS
Figure 2. Transfer Characteristics
102
101
100
0.2
175
25
Notes :
1. V = 0V
GS
2. 250s Pulse Test
0.4 0.6 0.8 1.0 1.2
V , Source-Drain voltage [V]
SD
1.4
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
V = 50V
10 DS
V = 80V
DS
8
6
4
2
 Note : I = 33A
D
0
0 5 10 15 20 25 30 35 40
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
©2000 Fairchild Semiconductor International
Rev. A, April 2000



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