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CY28352

Part Number	CY28352
Manufacturer	Cypress Semiconductor
Description	Differential Clock Buffer/Driver
Published	Aug 31, 2014
Detailed Description	CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features • Supports 333-MHz and 400-MHz DDR SDRAM •...
Datasheet	CY28352 PDF File

Overview

CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize output to clock input • Conforms to DDRI specification • Spread Aware™ for electromagnetic interference (EMI) reduction • 28-pin SSOP package Description This PLL clock buffer is designed for 2.
5-VDD and 2.
5-AVDD operation and differential output levels.
This device is a zero delay buffer that distributes a clock input CLKIN to six diff...

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