EFFECT TRANSISTOR. NP90N055NUK Datasheet

NP90N055NUK TRANSISTOR. Datasheet pdf. Equivalent

Part NP90N055NUK
Description MOS FIELD EFFECT TRANSISTOR
Feature Preliminary Data Sheet NP90N055MUK, NP90N055NUK MOS FIELD EFFECT TRANSISTOR R07DS0602EJ0100 Rev.1..
Manufacture Renesas
Datasheet
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Preliminary Data Sheet NP90N055MUK, NP90N055NUK MOS FIELD E NP90N055NUK Datasheet
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NP90N055NUK
Preliminary Data Sheet
NP90N055MUK, NP90N055NUK
MOS FIELD EFFECT TRANSISTOR
R07DS0602EJ0100
Rev.1.00
Jan 11, 2012
Description
These products are N-channel MOS Field Effect Transistors designed for high current switching applications.
Features
Super low on-state resistance
RDS(on) = 3.8 mMAX. (VGS = 10 V, ID = 45 A)
Low Ciss: Ciss = 4900 pF TYP. (VDS = 25 V)
Designed for automotive application and AEC-Q101 qualified
Ordering Information
Part No.
NP90N055MUK-S18-AY *1
NP90N055NUK-S18-AY *1
Lead Plating
Pure Sn (Tin)
Packing
Tube 50 p/tube
Note: *1 Pb-free (This product does not contain Pb in the external electrode)
Package
TO-220 (MP-25K)
TO-262 (MP-25SK)
Absolute Maximum Ratings (TA = 25°C)
Item
Symbol
Drain to Source Voltage (VGS = 0 V)
VDSS
Gate to Source Voltage (VDS = 0 V)
VGSS
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) *1
ID(DC)
ID(pulse)
Total Power Dissipation (TC = 25°C)
PT1
Total Power Dissipation (TA = 25°C)
PT2
Channel Temperature
Tch
Storage Temperature
Repetitive Avalanche Current *2
Repetitive Avalanche Energy *2
Tstg
IAR
EAR
Notes: *1 TC = 25°C, PW 10 s, Duty Cycle 1%
*2 RG = 25 , VGS = 20 0 V
Ratings
55
20
90
360
176
1.8
175
–55 to 175
38
144
Unit
V
V
A
A
W
W
°C
°C
A
mJ
Thermal Resistance
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
0.85 °C/W
83.3 °C/W
R07DS0602EJ0100 Rev.1.00
Jan 11, 2012
Page 1 of 6



NP90N055NUK
NP90N055MUK, NP90N055NUK
Electrical Characteristics (TA = 25°C)
Item
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance *1
Drain to Source On-state Resistance *1
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage *1
Reverse Recovery Time
Reverse Recovery Charge
Note: *1 Pulsed test
Symbol
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
MIN.
2.0
35
TYP.
3.0
70
3.15
4900
500
180
28
12
70
7
80
21
20
0.9
52
95
MAX.
1
100
4.0
3.80
7350
750
330
70
30
140
20
120
1.5
Unit
A
nA
V
S
m
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = 55 V, VGS = 0 V
VGS = 20 V, VDS = 0 V
VDS = VGS, ID = 250 A
VDS = 5 V, ID = 45 A
VGS = 10 V, ID = 45 A
VDS = 25 V
VGS = 0 V
f = 1 MHz
VDD = 28 V, ID = 45 A
VGS = 10 V
RG = 0
VDD = 44 V
VGS = 10 V
ID = 90 A
IF = 90 A, VGS = 0 V
IF = 90 A, VGS = 0 V
di/dt = 100 A/s
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 0 V
50 Ω
L
VDD
BVDSS
ID
VDD
IAS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
PG. RG
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VGS
VGS
Wave Form
10%
0
VDD
VDS
90%
VDS
VDS
Wave Form
0
td(on)
VGS 90%
90%
10% 10%
tr td(off)
tf
ton toff
R07DS0602EJ0100 Rev.1.00
Jan 11, 2012
Page 2 of 6





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