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BUFFER/LEVEL TRANSLATOR. SI53305 Datasheet

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BUFFER/LEVEL TRANSLATOR. SI53305 Datasheet






SI53305 TRANSLATOR. Datasheet pdf. Equivalent




SI53305 TRANSLATOR. Datasheet pdf. Equivalent





Part

SI53305

Description

1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53305 1:10 LOW JITTER UNIVERSAL BUFFE R/LEVEL TRANSLATOR WITH 2:1 INPUT MUX A ND INDIVIDUAL OE Features  10 diff erential or 20 LVCMOS outputs Low ou tput-output skew: <70 ps  Ultra-low additive jitter: 45 fs rms  Low pro pagation delay variation:  Wide fre quency range: <400 ps dc to 725 MHz  Independent VDD and VDDO :  Any -format input with pin selectabl.
Manufacture

Silicon Laboratories

Datasheet
Download SI53305 Datasheet


Silicon Laboratories SI53305

SI53305; e 1.8/2.5/3.3 V output formats: LVPECL, Low Power  Excellent power supply n oise LVPECL, LVDS, CML, HCSL, rejecti on (PSRR) LVCMOS  Selectable LVCMO S drive strength to  2:1 mux with h ot-swappable inputs tailor jitter and EMI performance  Glitchless input c lock switching (1 MHz to 725 MHz)  I ndividual output enable  Synchronous output enable  Small size: .


Silicon Laboratories SI53305

44-QFN (7 mm x 7 mm)  RoHS compliant, Pb-free  Industrial temperature ran ge: –40 to +85 °C Ordering Informat ion: See page 30. Applications  Hig h-speed clock distribution  Ethernet switch/router  Optical Transport Ne twork (OTN)  SONET/SDH  PCI Expre ss Gen 1/2/3  Storage  Telecom Industrial  Servers  Backplane clock distribution Description The Si53305 .


Silicon Laboratories SI53305

is an ultra low jitter ten output differ ential buffer with pin-selectable outpu t clock signal format and individual OE . The Si53305 features a 2:1 mux with g litchless switching, making it ideal fo r redundant clocking applications. The Si53305 utilizes Silicon Laboratories' advanced CMOS technology to fanout cloc ks from dc to 725 MHz with guaranteed l ow additive jitter.

Part

SI53305

Description

1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53305 1:10 LOW JITTER UNIVERSAL BUFFE R/LEVEL TRANSLATOR WITH 2:1 INPUT MUX A ND INDIVIDUAL OE Features  10 diff erential or 20 LVCMOS outputs Low ou tput-output skew: <70 ps  Ultra-low additive jitter: 45 fs rms  Low pro pagation delay variation:  Wide fre quency range: <400 ps dc to 725 MHz  Independent VDD and VDDO :  Any -format input with pin selectabl.
Manufacture

Silicon Laboratories

Datasheet
Download SI53305 Datasheet




 SI53305
Si53305
1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE
Features
10 differential or 20 LVCMOS outputsLow output-output skew: <70 ps
Ultra-low additive jitter: 45 fs rms Low propagation delay variation:
Wide frequency range:
<400 ps
dc to 725 MHz
Independent VDD and VDDO :
Any-format input with pin selectable 1.8/2.5/3.3 V
output formats: LVPECL, Low Power Excellent power supply noise
LVPECL, LVDS, CML, HCSL,
rejection (PSRR)
LVCMOS
Selectable LVCMOS drive strength to
2:1 mux with hot-swappable inputs
tailor jitter and EMI performance
Glitchless input clock switching
(1 MHz to 725 MHz)
Individual output enable
Synchronous output enable
Small size: 44-QFN (7 mm x 7 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Ordering Information:
See page 30.
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53305 is an ultra low jitter ten output differential buffer with pin-selectable
output clock signal format and individual OE. The Si53305 features a 2:1 mux with
glitchless switching, making it ideal for redundant clocking applications. The
Si53305 utilizes Silicon Laboratories' advanced CMOS technology to fanout
clocks from dc to 725 MHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53305 features minimal cross-talk and
provides superior supply noise rejection, simplifying low jitter clock distribution in
noisy environments. Independent core and output bank supply pins provide
integrated level translation without the need for external circuitry.
Functional Block Diagram
Pin Assignments
Si53305
OE2 1
SFOUT[0] 2
OE1 3
Q2 4
Q2 5
GND 6
Q1 7
Q1 8
Q0 9
Q0 10
OE0 11
GND
PAD
33 OE7
32 SFOUT[1]
31 OE8
30 Q7
29 Q7
28 NC
27 Q8
26 Q8
25 Q9
24 Q9
23 OE9
Patents pending
VREF
Vref
Generator
Power
Supply
Filtering
CLK0
CLK0
CLK1
CLK1
CLK_SEL
Switching
Logic
VDDOA
OE[0:4]
Q0, Q1, Q2, Q3, Q4
Q0, Q1, Q2, Q3, Q4
SFOUT[1:0]
VDDOB
OE[5:9]
Q5, Q6, Q7, Q8, Q9
Q5, Q6, Q7, Q8, Q9
Rev. 1.0 9/15
Copyright © 2015 by Silicon Laboratories
Si53305




 SI53305
Si53305
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3. Voltage Reference (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5. Glitchless Clock Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6. Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8. Power Supply (VDD and VDDOX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.9. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.10. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.11. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.12. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.13. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3. Pin Description: 44-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1. 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.1. 7x7 mm 44-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1. Si53305 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2 Rev. 1.0




 SI53305
Si53305
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
TA
VDD
Test Condition
LVDS, CML
Min Typ Max Unit
–40 —
85 °C
1.71 1.8 1.89 V
2.38 2.5 2.63 V
2.97 3.3 3.63 V
LVPECL, low power LVPECL,
2.38
2.5
2.63 V
LVCMOS
2.97 3.3 3.63 V
HCSL
2.97 3.3 3.63 V
Output Buffer Supply
Voltage*
VDDOX
LVDS, CML, LVCMOS
1.71 1.8 1.89 V
2.38 2.5 2.63 V
2.97 3.3 3.63 V
LVPECL, low power LVPECL 2.38 2.5 2.63 V
2.97 3.3 3.63 V
HCSL
2.97 3.3 3.63 V
*Note: Core supply VDD and output buffer supplies VDDO are independent. LVCMOS clock input is not supported for VDD =
1.8V but is supported for LVCMOS clock output for VDDOX = 1.8V. LVCMOS outputs at 1.5V and 1.2V can be
supported via a simple resistor divider network. See “2.9.1. LVCMOS Output Termination To Support 1.5V and 1.2V”
Table 2. Input Clock Specifications
(VDD=1.8 V 5%, 2.5 V 5%, or 3.3 V 10%, TA=–40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Differential Input Common
Mode Voltage
VCM
VDD = 2.5 V5%, 3.3 V10%
0.05
— —V
Differential Input Swing
(peak-to-peak)
VIN
0.2 — 2.2 V
LVCMOS Input High Volt-
age
VIH
VDD = 2.5 V5%, 3.3 V10% VDD x 0.7
—V
LVCMOS Input Low Volt- VIL VDD = 2.5 V5%, 3.3 V10%
age
— VDD x V
0.3
Input Capacitance
CIN CLK0 and CLK1 pins with — 5 — pF
respect to GND
Rev. 1.0
3



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