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BUFFER/LEVEL TRANSLATOR. SI53307 Datasheet

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BUFFER/LEVEL TRANSLATOR. SI53307 Datasheet






SI53307 TRANSLATOR. Datasheet pdf. Equivalent




SI53307 TRANSLATOR. Datasheet pdf. Equivalent





Part

SI53307

Description

2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53307 2:2 LOW JITTER UNIVERSAL BUFFER /LEVEL TRANSLATOR Features  2 diff erential or 4 LVCMOS outputs  2:1 in put mux with glitchless input  Ultr a-low additive jitter: 45 fs rms clock switching  Wide frequency range: 1 to 725 MHz  Independent VDD and VDD O :  Any-format input with pin sele ctable 1.8/2.5/3.3 V output formats: L VPECL, low power  Small size:.
Manufacture

Silicon Laboratories

Datasheet
Download SI53307 Datasheet


Silicon Laboratories SI53307

SI53307; 16-QFN (3 mm x 3 mm) LVPECL, LVDS, CML , HCSL,  RoHS compliant, Pb-free L VCMOS  Synchronous output enable Industrial temperature range: –40 t o +85 °C Applications  High-speed clock distribution  Ethernet switch/ router  Optical Transport Network (O TN)  SONET/SDH  PCI Express Gen 1 /2/3  Storage  Telecom  Indus trial  Servers  Backplane clock distribut.


Silicon Laboratories SI53307

ion Description The Si53307 is an ultra -low jitter two output differential buf fer with pin-selectable output clock si gnal format and 2:1 input clock mux. Th e Si53307 utilizes Silicon Labs' advanc ed CMOS technology to fanout clocks fro m 1 to 725 MHz with guaranteed low addi tive jitter, low skew, and low propagat ion delay variability. The Si53307 feat ures minimal cross.


Silicon Laboratories SI53307

-talk and provides superior supply noise rejection, simplifying low jitter cloc k distribution in noisy environments. I ndependent core and output bank supply pins provide integrated level translati on without the need for external circui try. Functional Block Diagram Ordering Information: See page 26. Pin Assignme nts OE GND CLK_SEL SFOUT0 13 14 15 16 VDD 1 CLK1 2 CLK.

Part

SI53307

Description

2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53307 2:2 LOW JITTER UNIVERSAL BUFFER /LEVEL TRANSLATOR Features  2 diff erential or 4 LVCMOS outputs  2:1 in put mux with glitchless input  Ultr a-low additive jitter: 45 fs rms clock switching  Wide frequency range: 1 to 725 MHz  Independent VDD and VDD O :  Any-format input with pin sele ctable 1.8/2.5/3.3 V output formats: L VPECL, low power  Small size:.
Manufacture

Silicon Laboratories

Datasheet
Download SI53307 Datasheet




 SI53307
Si53307
2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR
Features
2 differential or 4 LVCMOS outputs 2:1 input mux with glitchless input
Ultra-low additive jitter: 45 fs rms
clock switching
Wide frequency range: 1 to 725 MHz Independent VDD and VDDO :
Any-format input with pin selectable 1.8/2.5/3.3 V
output formats: LVPECL, low power Small size: 16-QFN (3 mm x 3 mm)
LVPECL, LVDS, CML, HCSL,
RoHS compliant, Pb-free
LVCMOS
Synchronous output enable
Industrial temperature range:
–40 to +85 °C
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53307 is an ultra-low jitter two output differential buffer with pin-selectable
output clock signal format and 2:1 input clock mux. The Si53307 utilizes Silicon
Labs' advanced CMOS technology to fanout clocks from 1 to 725 MHz with
guaranteed low additive jitter, low skew, and low propagation delay variability. The
Si53307 features minimal cross-talk and provides superior supply noise rejection,
simplifying low jitter clock distribution in noisy environments. Independent core
and output bank supply pins provide integrated level translation without the need
for external circuitry.
Functional Block Diagram
Ordering Information:
See page 26.
Pin Assignments
VDD 1
CLK1 2
CLK1 3
GND 4
GND
PAD
12 Q0
11 Q0
10 Q1
9 Q1
Patents pending
Rev. 1.0 11/14
Copyright © 2014 by Silicon Laboratories
Si53307




 SI53307
Si53307
2 Rev. 1.0




 SI53307
TABLE OF CONTENTS
Si53307
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4. Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5. Glitchless Clock Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7. Power Supply (VDD and VDDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.9. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.10. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.11. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3. Pin Description: 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1. Si53307 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Rev. 1.0
3



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