DatasheetsPDF.com

BUFFER/LEVEL TRANSLATOR. SI53312 Datasheet

DatasheetsPDF.com

BUFFER/LEVEL TRANSLATOR. SI53312 Datasheet






SI53312 TRANSLATOR. Datasheet pdf. Equivalent




SI53312 TRANSLATOR. Datasheet pdf. Equivalent





Part

SI53312

Description

1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53312 1:10 LOW JITTER UNIVERSAL BUFFE R/LEVEL TRANSLATOR WITH 2:1 INPUT MUX ( <1.25 GHZ) Features  10 differenti al or 20 LVCMOS outputs Low output-o utput skew: <70 ps  Ultra-low addit ive jitter: 45 fs rms  Low propagati on delay variation:  Wide frequency range: <400 ps dc to 1.25 GHz  I ndependent VDD and VDDO :  Any-form at input with pin selectable 1.8.
Manufacture

Silicon Laboratories

Datasheet
Download SI53312 Datasheet


Silicon Laboratories SI53312

SI53312; /2.5/3.3 V output formats: LVPECL, Low Power  Excellent power supply noise LVPECL, LVDS, CML, HCSL, rejection (P SRR) LVCMOS  Selectable LVCMOS dri ve strength to  2:1 mux with hot-sw appable inputs tailor jitter and EMI p erformance  Asynchronous output ena ble  Small size: 44-QFN (7 mm x 7 m m)  Output clock division: /1, /2, /4 (/2 and /4 for dc to 725 MH.


Silicon Laboratories SI53312

z)  RoHS compliant, Pb-free  Indu strial temperature range: –40 to +85 °C Ordering Information: See page 28 . Applications  High-speed clock di stribution  Ethernet switch/router Optical Transport Network (OTN)  SONET/SDH  PCI Express Gen 1/2/3 Storage  Telecom  Industrial Servers  Backplane clock distribut ion Description The Si53312 is an ultra low .


Silicon Laboratories SI53312

jitter ten output differential buffer wi th pin-selectable output clock signal f ormat and divider selection. The Si5331 2 features a 2:1 mux, making it ideal f or redundant clocking applications. The Si53312 utilizes Silicon Laboratories' advanced CMOS technology to fanout clo cks from dc to 1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay.

Part

SI53312

Description

1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53312 1:10 LOW JITTER UNIVERSAL BUFFE R/LEVEL TRANSLATOR WITH 2:1 INPUT MUX ( <1.25 GHZ) Features  10 differenti al or 20 LVCMOS outputs Low output-o utput skew: <70 ps  Ultra-low addit ive jitter: 45 fs rms  Low propagati on delay variation:  Wide frequency range: <400 ps dc to 1.25 GHz  I ndependent VDD and VDDO :  Any-form at input with pin selectable 1.8.
Manufacture

Silicon Laboratories

Datasheet
Download SI53312 Datasheet




 SI53312
Si53312
1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX (<1.25 GHZ)
Features
10 differential or 20 LVCMOS outputsLow output-output skew: <70 ps
Ultra-low additive jitter: 45 fs rms Low propagation delay variation:
Wide frequency range:
<400 ps
dc to 1.25 GHz
Independent VDD and VDDO :
Any-format input with pin selectable 1.8/2.5/3.3 V
output formats: LVPECL, Low Power Excellent power supply noise
LVPECL, LVDS, CML, HCSL,
rejection (PSRR)
LVCMOS
Selectable LVCMOS drive strength to
2:1 mux with hot-swappable inputs
tailor jitter and EMI performance
Asynchronous output enable
Small size: 44-QFN (7 mm x 7 mm)
Output clock division: /1, /2, /4
(/2 and /4 for dc to 725 MHz)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Ordering Information:
See page 28.
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53312 is an ultra low jitter ten output differential buffer with pin-selectable
output clock signal format and divider selection. The Si53312 features a 2:1 mux,
making it ideal for redundant clocking applications. The Si53312 utilizes Silicon
Laboratories' advanced CMOS technology to fanout clocks from dc to 1.25 GHz
with guaranteed low additive jitter, low skew, and low propagation delay variability.
The Si53312 features minimal cross-talk and provides superior supply noise
rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
without the need for external circuitry.
Pin Assignments
Si53312
DIVA 1
SFOUTA[1] 2
SFOUTA[0] 3
Q2
Q2
GND
Q1
4
5
6
7
Q1 8
Q0 9
Q0 10
NC 11
GND
PAD
33 DIVB
32 SFOUTB[1]
31 SFOUTB[0]
30 Q7
29 Q7
28 NC
27 Q8
26 Q8
25 Q9
24 Q9
23 CLK_SEL
Patents pending
Functional Block Diagram
VREF
CLK0
/CLK0
CLK1
/CLK1
CLK_SEL
Vref
Generator
Power
Supply
Filtering
DivA
Switching
Logic
DivB
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2, Q3, Q4
Q0, Q1, Q2, Q3, Q4
DIVB
VDDOB
SFOUTB[1:0]
OEB
Q5, Q6, Q7, Q8, Q9
Q5, Q6, Q7, Q8, Q9
Rev. 1.0 9/15
Copyright © 2015 by Silicon Laboratories
Si53312




 SI53312
Si53312
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3. Voltage Reference (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6. Flexible Output Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7. Power Supply (VDD and VDDOX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.9. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.10. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.11. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.12. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.13. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3. Pin Description: 44-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1. 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.1. 7x7 mm 44-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1. Si53312 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2 Rev. 1.0




 SI53312
Si53312
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
TA
VDD
Test Condition
LVDS, CML
Min Typ Max Unit
–40 —
85 °C
1.71 1.8 1.89 V
2.38 2.5 2.63 V
2.97 3.3 3.63 V
LVPECL, low power LVPECL,
2.38
2.5
2.63 V
LVCMOS
2.97 3.3 3.63 V
HCSL
2.97 3.3 3.63 V
Output Buffer Supply
Voltage*
VDDOX
LVDS, CML, LVCMOS
1.71 1.8 1.89 V
2.38 2.5 2.63 V
2.97 3.3 3.63 V
LVPECL, low power LVPECL 2.38 2.5 2.63 V
2.97 3.3 3.63 V
HCSL
2.97 3.3 3.63 V
*Note: Core supply VDD and output buffer supplies VDDO are independent. LVCMOS clock input is not supported for VDD =
1.8V but is supported for LVCMOS clock output for VDDOX = 1.8V. LVCMOS outputs at 1.5V and 1.2V can be
supported via a simple resistor divider network. See “2.8.1. LVCMOS Output Termination To Support 1.5 V and 1.2 V”
Table 2. Input Clock Specifications
(VDD=1.8 V 5%, 2.5 V 5%, or 3.3 V 10%, TA=–40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Differential Input Common
Mode Voltage
VCM
VDD = 2.5 V5%, 3.3 V10%
0.05
— —V
Differential Input Swing
(peak-to-peak)
VIN
0.2 — 2.2 V
LVCMOS Input High
Voltage
VIH VDD = 2.5 V5%, 3.3 V10% VDD x 0.7 —
—V
LVCMOS Input Low
Voltage
VIL VDD = 2.5 V5%, 3.3 V10%
— VDD x V
0.3
Input Capacitance
CIN CLK0 and CLK1 pins with — 5 — pF
respect to GND
Rev. 1.0
3



Recommended third-party SI53312 Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)