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BUFFER/LEVEL TRANSLATOR. SI53313 Datasheet

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BUFFER/LEVEL TRANSLATOR. SI53313 Datasheet






SI53313 TRANSLATOR. Datasheet pdf. Equivalent




SI53313 TRANSLATOR. Datasheet pdf. Equivalent





Part

SI53313

Description

DUAL 1:5 LOW-JITTER ANY-FORMAT BUFFER/LEVEL TRANSLATOR



Feature


Si53313 DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/LEVEL TRANSLATOR (<1.25 GHZ) F eatures  2 independent banks of 5x  Output clock division: /1, /2, /4 (dc to differential outputs 725 MHz f or /2 and /4)  Ultra-low additive j itter: 45 fs rms  Wide frequency ran ge:  Independent VDD and VDDO: 1.8/ 2.5/3.3 V dc to 1.25 GHz  Excellen t power supply noise  Any-fo.
Manufacture

Silicon Laboratories

Datasheet
Download SI53313 Datasheet


Silicon Laboratories SI53313

SI53313; rmat input with pin selectable rejection (PSRR) output formats: LVPECL, Low Po wer  Small size: 44-QFN (7 mm x 7 mm ) LVPECL, LVDS, CML, HCSL,  RoHS c ompliant, Pb-free LVCMOS  Industri al temperature range:  Asynchronous output enable –40 to +85 °C  L ow output-output skew: <70 ps Applicat ions  High-speed clock distribution  Ethernet switch/router  Optica.


Silicon Laboratories SI53313

l Transport Network (OTN)  SONET/SDH  PCI Express Gen 1/2/3  Storage  Telecom  Industrial  Servers  Backplane clock distribution Order ing Information: See page 27. Pin Assig nments Si53313 VDDOA Q3 Q3 Q4 Q4 GND Q 5 Q5 Q6 Q6 VDDOB 34 35 36 37 38 39 40 41 42 43 44 Description DIVA 1 33 DI VB The Si53313 is an ultra low jitter dual 1:5 differential buffer wit.


Silicon Laboratories SI53313

h pin-selectable SFOUTA[1] 2 SFOUTA[0] 3 32 SFOUTB[1] 31 SFOUTB[0] output cl ock signal format and divider selection . The Si53313 utilizes Silicon Q2 4 3 0 Q7 Laboratories' advanced CMOS techn ology to fanout clocks from dc to 1.25 GHz with guaranteed low additive jitter , low skew, and low propagation delay v ariability. Q2 GND Q1 5 6 7 GND PAD 29 Q7 28 NC 27 Q8.

Part

SI53313

Description

DUAL 1:5 LOW-JITTER ANY-FORMAT BUFFER/LEVEL TRANSLATOR



Feature


Si53313 DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/LEVEL TRANSLATOR (<1.25 GHZ) F eatures  2 independent banks of 5x  Output clock division: /1, /2, /4 (dc to differential outputs 725 MHz f or /2 and /4)  Ultra-low additive j itter: 45 fs rms  Wide frequency ran ge:  Independent VDD and VDDO: 1.8/ 2.5/3.3 V dc to 1.25 GHz  Excellen t power supply noise  Any-fo.
Manufacture

Silicon Laboratories

Datasheet
Download SI53313 Datasheet




 SI53313
Si53313
DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/LEVEL
TRANSLATOR (<1.25 GHZ)
Features
2 independent banks of 5x
Output clock division: /1, /2, /4 (dc to
differential outputs
725 MHz for /2 and /4)
Ultra-low additive jitter: 45 fs rms
Wide frequency range:
Independent VDD and VDDO:
1.8/2.5/3.3 V
dc to 1.25 GHz
Excellent power supply noise
Any-format input with pin selectable rejection (PSRR)
output formats: LVPECL, Low Power Small size: 44-QFN (7 mm x 7 mm)
LVPECL, LVDS, CML, HCSL,
RoHS compliant, Pb-free
LVCMOS
Industrial temperature range:
Asynchronous output enable
–40 to +85 °C
Low output-output skew: <70 ps
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Ordering Information:
See page 27.
Pin Assignments
Si53313
Description
DIVA 1
33 DIVB
The Si53313 is an ultra low jitter dual 1:5 differential buffer with pin-selectable
SFOUTA[1] 2
SFOUTA[0] 3
32 SFOUTB[1]
31 SFOUTB[0]
output clock signal format and divider selection. The Si53313 utilizes Silicon
Q2 4
30 Q7
Laboratories' advanced CMOS technology to fanout clocks from dc to 1.25 GHz
with guaranteed low additive jitter, low skew, and low propagation delay variability.
Q2
GND
Q1
5
6
7
GND
PAD
29 Q7
28 NC
27 Q8
The Si53313 features minimal cross-talk and provides superior supply noise
Q1 8
Q0 9
26 Q8
25 Q9
rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
Q0 10
NC 11
24 Q9
23 NC
without the need for external circuitry.
Functional Block Diagram
Patents pending
VREF
CLK0
CLK0
Vref
Generator
Power
Supply
Filtering
DivA
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2, Q3, Q4
Q0, Q1, Q2, Q3, Q 4
CLK1
CLK1
DivB
DIVB
VDDOB
SFOUTB[1:0]
OEB
Q5, Q 6, Q7, Q8, Q9
Q5, Q6, Q7, Q8, Q9
Rev. 1.0 12/15
Copyright © 2015 by Silicon Laboratories
Si53313




 SI53313
Si53313
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3. Voltage Reference (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5. Flexible Output Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6. Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7. Power Supply (VDD and VDDOX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.8. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.9. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.10. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.11. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.12. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3. Pin Description: 44-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1. 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.1. 7x7 mm 44-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1. Si53313 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2 Rev. 1.0




 SI53313
Si53313
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
TA
VDD
Test Condition
LVDS, CML
Min Typ Max Unit
–40 —
85 °C
1.71 1.8 1.89 V
2.38 2.5 2.63 V
2.97 3.3 3.63 V
LVPECL, low power LVPECL,
2.38
2.5
2.63 V
LVCMOS
2.97 3.3 3.63 V
HCSL
2.97 3.3 3.63 V
Output Buffer Supply
Voltage*
VDDOX
LVDS, CML, LVCMOS
1.71 1.8 1.89 V
2.38 2.5 2.63 V
2.97 3.3 3.63 V
LVPECL, low power LVPECL 2.38 2.5 2.63 V
2.97 3.3 3.63 V
HCSL
2.97 3.3 3.63 V
*Note: Core supply VDD and output buffer supplies VDDO are independent. LVCMOS clock input is not supported for VDD =
1.8V but is supported for LVCMOS clock output for VDDOX = 1.8V. LVCMOS outputs at 1.5V and 1.2V can be
supported via a simple resistor divider network. See “2.8.1. LVCMOS Output Termination To Support 1.5 V and 1.2 V”
Table 2. Input Clock Specifications
(VDD=1.8 V 5%, 2.5 V 5%, or 3.3 V 10%, TA=–40 to 85 °C)
Parameter
Differential Input Com-
mon Mode Voltage
Differential Input Swing
(peak-to-peak)
LVCMOS Input High
Voltage
LVCMOS Input Low
Voltage
Input Capacitance
Symbol
Test Condition
VCM
VDD = 2.5 V5%, 3.3 V10%
VIN
VIH VDD = 2.5 V5%, 3.3 V10%
VIL VDD = 2.5 V5%, 3.3 V10%
CIN CLK0 and CLK1 pins with
respect to GND
Min
0.05
0.2
VDD x 0.7
Typ Max Unit
— —V
— 2.2 V
— —V
— VDD x 0.3 V
5 — pF
Rev. 1.0
3



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