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CY7C1381D

Part Number	CY7C1381D
Manufacturer	Cypress
Description	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Published	Oct 2, 2016
Detailed Description	Not Recommended for New Designs. CY7C1381D CY7C1383D CY7C1383F 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM 18-Mbit (...
Datasheet	CY7C1381D PDF File

Overview

Not Recommended for New Designs.
CY7C1381D CY7C1383D CY7C1383F 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM Features ■ Supports 133 MHz bus operations ■ 512K × 36 and 1M × 18 common I/O ■ 3.
3 V core power supply (VDD) ■ 2.
5 V or 3.
3 V I/O supply (VDDQ) ■ Fast clock-to-output time ❐ 6.
5 ns (133 MHz version) ■ Provides high performance 2-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ CY7C1381D available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package.
CY7C1383D available in JEDEC-standard Pb-free 100-pin TQFP.
CY7C1383F available in non Pb-free 165-ball FBGA package.
■ IEEE 1149.
1 JTAG-Compatible Boundary Scan ■ ZZ sleep mode option Functional Description The CY7C1381D/CY7C1383D/CY7C1383F is a 3.
3 V, 512K × 36 and 1M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic.
Maximum access delay from clock rise is 6.
5 ns (133 MHz version).
A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.
All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).
The synchronous inputs include all addresses, all data inputs, address pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWx, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ pin.
The CY7C1381D/CY7C1383D/CY7C1383F allows interleaved or linear burst sequences, selected by the MODE input pin.
A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence.
Burst accesses can be initiated with the processor address strobe (ADSP...

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