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IDCI3

AMI
Part Number IDCI3
Manufacturer AMI
Description CMOS Gate Array
Published Mar 12, 2018
Detailed Description ,'&, ® $0,+*  PLFURQ &026 *DWH $UUD\ Description IDCI3 is an inverting, CMOS-level input buffer piece. Logic Sym...
Datasheet PDF File IDCI3 PDF File

IDCI3
IDCI3

Overview
,'&, ® $0,+*  PLFURQ &026 *DWH $UUD\ Description IDCI3 is an inverting, CMOS-level input buffer piece.
Logic Symbol Truth Table Pin Loading IDCI3 QC P PADM D PADM QC LH HL Load PADM 4.
90 pF HDL Syntax Verilog IDCI3 inst_name (QC, PADM); VHDL.
.
inst_name: IDCI3 port map (QC, PADM); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation.
Value TBD 12.
7 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.
0V, Typical Process Delay (ns) From To Parameter 1 PADM QC tPLH tPHL 0.
62 0.
72 Delay will vary with input conditions.
See page 2-17 for interconnect estimates.
Number of E...


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