NPN/PNP Silicon Digital Transistor Array Preliminary data
Description
SEMD2
NPN/PNP Silicon Digital Transistor Array Preliminary data Switching circuit, inverter, interface circuit, driver circuit Two (galvanic) internal isolated NPN/PNP Transistors in one package Built in bias resistor (R1=22kΩ, R2 =22kΩ) Tape loading orientation
Top View
3 2 1
4 5 3 6 1 2
Marking on SOT666 package (for example W R) corresponds to pin...
Infineon Technologies AG
SEMD2 PDF File
Similar Datasheet