(PALCE610 / PALCE600) EE CMOS High Performance Programmable Array Logic
Description
USE GAL DEVICES FOR NEW DESIGNS
FINAL COM’L: H-15/25
CONNECTION DIAGRAMS Top View SKINNYDIP
I/O9
PLCC/LCC
CLK1 VCC I I I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I CLK2
12950G-2
VCC
EE CMOS High Performance Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s Lattice/Vantis Programmable Array Logic (PAL) architecture s Electrically-erasable CMOS technolog...
