5V 1M x 16 CMOS DRAM
Description
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Organization: 1,048,576 words × 16 bits High speed
- 45/50/60 ns RAS access time - 20/20/25 ns hyper page cycle time - 10/12/15 ns CAS access time
1024 refresh cycles, 16 ms refresh interval
- RAS-only or CAS-before-RAS refresh Read-modify-write
TTL-compatible, three-state DQ JEDEC stan...
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