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CY2DP3110
Differential Clock/Data Fanout Buffer
Description
www.DataSheet4U.com FastEdge™ Series CY2DP3110 1 of 2:10 Differential Clock/Data Fanout Buffer Features Ten ECL/PECL differential outputs One ECL/PECL differential or single-ended inputs (CLKA) One HSTL differential or single-ended inputs (CLKB) Hot-swappable/-insertable 50 ps output-to-output skew 150 ps device-to-device skew 400 ps propagat...
Cypress Semiconductor
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