Preliminary
PLL102-109
Programmable DDR Zero Delay Clock Driver
FEATURES
PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. Distributes one clock Input to one bank of six differential outputs. Track spread spectrum clocking for EMI reduction. Programmable delay between CLK_INT and CLK[T/C] from –0.8ns to +3.1ns by p...
