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CY7C1219H

1-Mbit (32K x 36) Pipelined DCD Sync SRAM

Description

CY7C1219H www.DataSheet4U.com 1-Mbit (32K x 36) Pipelined DCD Sync SRAM Features Registered inputs and outputs for pipelined operation Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state 32K × 36-bit common I/O architecture 3.3V core power supply (VDD) 2.5V/3.3V I/O power supply (VDDQ) Fast clock-to-output times ...

Cypress Semiconductor

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