DatasheetsPDF.com

M36L0R8060B1

STMicroelectronics
Part Number M36L0R8060B1
Manufacturer STMicroelectronics
Description Multi-Chip Package
Published Apr 24, 2010
Detailed Description www.DataSheet4U.com M36L0R8060T1 M36L0R8060B1 256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Bu...
Datasheet PDF File M36L0R8060B1 PDF File

M36L0R8060B1
M36L0R8060B1

Overview
www.
DataSheet4U.
com M36L0R8060T1 M36L0R8060B1 256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Burst) PSRAM, 1.
8V Supply, Multi-Chip Package FEATURES SUMMARY MULTI-CHIP PACKAGE – 1 die of 256 Mbit (16Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory – 1 die of 64 Mbit (4Mb x16) Pseudo SRAM ■ SUPPLY VOLTAGE – VDDF = VCCP = VDDQF = 1.
7 to 1.
95V – VPPF = 9V for fast program (12V tolerant) ■ ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code M36L0R8060T1: 880Dh – Bottom Device Code M36L0R8060B1: 880Eh ■ PACKAGE – Compliant with Lead-Free Soldering Processes – Lead-Free Versions FLASH MEMORY ■ SYNCHRONOUS / ASYNCHRONOUS READ – Synchronous Burst Read mode: 54MHz – Asynchronous Page Read mode – Random Access: 85ns ■ SYNCHRONOUS BURST READ SUSPEND ■ PROGRAMMING TIME – 10µs typical Word program time using Buffer Enhanced Factory Program command ■ MEMORY ORGANIZATION – Multiple Bank Memory Array: 16 Mbit Banks – Parameter Blocks (Top or Bottom location) ■ DUAL OPERATIONS – program/erase in one Bank while read in others – No delay between read and write operations ■ SECURITY – 64 bit unique device number – 2112 bit user programmable OTP Cells ■ Figure 1.
Package FBGA TFBGA88 (ZAQ) 8 x 10mm BLOCK LOCKING – All blocks locked at power-up – Any combination of blocks can be locked with zero latency – WPF for Block Lock-Down – Absolute Write Protection with VPPF = VSS ■ COMMON FLASH INTERFACE (CFI) ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK PSRAM ■ ACCESS TIME: 70ns ■ ASYNCHRONOUS PAGE READ – Page Size: 16 words – Subsequent read within page: 20ns ■ LOW POWER FEATURES – Temperature Compensated Refresh (TCR) – Partial Array Refresh (PAR) – Deep Power-Down (DPD) Mode ■ SYNCHRONOUS BURST READ/WRITE ■ June 2005 1/18 www.
DataSheet4U.
com M36L0R8060T1, M36L0R8060B1 TABLE OF CONTENTS FEATURES SUMMARY .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1 FLASH MEMORY .
.
.
.
...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)