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PZ5032

Philips
Part Number PZ5032
Manufacturer Philips
Description 32 macrocell CPLD
Published May 5, 2014
Detailed Description INTEGRATED CIRCUITS PZ5032 32 macrocell CPLD Product specification IC27 Data Handbook 1997 Feb 20 Philips Semiconducto...
Datasheet PDF File PZ5032 PDF File

PZ5032
PZ5032

Overview
INTEGRATED CIRCUITS PZ5032 32 macrocell CPLD Product specification IC27 Data Handbook 1997 Feb 20 Philips Semiconductors Free Datasheet http://www.
Datasheet4U.
com Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 FEATURES • Industry’s first TotalCMOS™ PLD – both CMOS design and • Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed process technologies DESCRIPTION The PZ5032 CPLD (Complex Programmable Logic Device) is the first in a family of Fast Zero Power (FZP™) CPLDs from Philips Semiconductors.
These devices combine high speed and zero power in a 32 macrocell CPLD.
With the FZP™ design technique, the PZ5032 offers true pin-to-pin speeds of 6ns, while simultaneously delivering power that is less than 75µA at standby without the need for ‘turbo bits’ or other power down schemes.
By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD – 70% lower at 50MHz.
These devices are the first TotalCMOS™ PLDs, as they use both a CMOS process technology and the patented full CMOS FZP™ design technique.
For 3V applications, Philips also offers the high speed PZ3032 CPLD that offers these features in a full 3V implementation.
The Philips FZP™ CPLDs introduce the new patent-pending XPLA™ (eXtended Programmable Logic Array) architecture.
The XPLA™ architecture combines the best features of both PLA and PAL™ type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts.
The XPLA™ structure in each logic block provides a fast 6ns PAL™ path with 5 dedicated product terms per output.
This PAL™ path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product ter...


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