72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burs.
t of 2) CIO Synchronous SRAMs (2.
5 Cycle Read Latency) Advanced Information May 2009 Features • 2M x 36 or 4M x 18.
• On-chip delay-locked loop (DLL) for wide data valid window.
• Common data input/output bus.
• Synchronous pipeline read with self-timed late write operation.
• Double data rate (DDR-IIP) interface for read and write input ports.
• Fixed 2-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and control registering at rising edges only.
• Industrial temperature available upon request.
• Two echo clocks (CQ and CQ) that are delivered simultaneously with data.
• +1.
8V core power suppl...

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