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IS61DDPB22M36A1

Part Number	IS61DDPB22M36A1
Manufacturer	Integrated Silicon Solution
Description	72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
Published	Jul 25, 2016
Detailed Description	IS61DDPB24M18A/A1/A2 IS61DDPB22M36A/A1/A2 4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Latenc...
Datasheet	IS61DDPB22M36A1 PDF File

Overview

IS61DDPB24M18A/A1/A2 IS61DDPB22M36A/A1/A2 4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (2.
5 Cycle Read Latency) ADVANCED INFORMATION JULY 2012 FEATURES DESCRIPTION  2Mx36 and 4Mx18 configuration available.
 On-chip Delay-Locked Loop (DLL) for wide data valid window.
 Common I/O read and write ports.
 Synchronous pipeline read with self-timed late write operation.
 Double Data Rate (DDR) interface for read and write input ports.
 2.
5 cycle read latency.
 Fixed 2-bit burst for read and write operations.
 Clock stop support.
 Two input clocks (K and K#) for address and control registering at rising edges only.
 Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
 +1.
8V core power supply and 1.
5, 1.
8V VDDQ, used with 0.
75, 0.
9V VREF.
 HSTL input and output interface.
 Registered addresses, write and read controls, byte writes, data in, and data outputs.
 Full data coherency.
 Boundary scan using limited set of JTAG 1149.
1 functions.
 Byte write capability.
 Fine ball grid array (FBGA) package: 13mm x 15mm & 15mm x 17mm body size 165-ball (11 x 15) array  Programmable impedance output drivers via 5x user-supplied precision resistor.
 Data Valid Pin (QVLD).
 ODT (On Die Termination) feature is supported optionally on data input, K/K#, and BWx#.
 The end of top mark (A/A1/A2) is to define options.
IS61DDPB22M36A : Don’t care ODT function and pin connection IS61DDPB22M36A1 : Option1 IS61DDPB22M36A2 : Option2 Refer to more detail description at page 6 for each ODT option.
The 72Mb IS61DDPB22M36A/A1/A2 and IS61DDPB24M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices.
These SRAMs have a common I/O bus.
The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs.
Read and write addresses are register...

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