CY2XP304 High-Frequency Programmable PECL Clock Generation Module Features • Period jitter peak-peak 125MHz(max.
) = 55 ps • Four low-skew LVPECL outputs • Phase-locked loop (PLL) multiplier select • Serially-configurable multiply ratios • Eight-bit feedback counter and six-bit reference counter for high accuracy • HSTL inputs—HSTL-to-LVPECL level translation • 125- to 500-MHz output range for high-speed applications • High-speed PLL bypass mode to 1.
5 GHz • 36-VFBGA, 6 × 8 × 1 mm • 3.
3V operation Block Diagram PLL_MULT CLK0 CLK0B CLK1 XIN XOUT SER CLK SER DATA INA INAB CLK_SEL XTAL OSCILLATOR PLL xM 0 1 CLK1B CLK2 CLK2B CLK3 CLK3B Pin Configuration C Y 2 X P 3 0 4 3 6 V F B G A P IN C O...

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