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CY2XP306

Part Number	CY2XP306
Manufacturer	Cypress Semiconductor
Description	High-frequency Programmable PECL Clock Generation Module
Published	Jul 30, 2011
Detailed Description	PRELIMINARY CY2XP306 High-frequency Programmable PECL Clock Generation Module Features • 60 ps typical Cycle-to-Cycle ...
Datasheet	CY2XP306 PDF File

Overview

PRELIMINARY CY2XP306 High-frequency Programmable PECL Clock Generation Module Features • 60 ps typical Cycle-to-Cycle Jitter • 30 ps typical Output-Output Skew • Phase-locked loop (PLL) multiplier select • LVTTL or XO Input; Six LVPECL Outputs • Selectable Output Divider (/2) • 1–133 MHz Input Frequency Range • 62.
5–500 MHz Output Frequency Range • 36-pin VFBGA, 6 × 8 × 1 mm • 3.
3V operation • Serially Configurable Multiply Ratios Block Diagram QA1 FSELA QA1# PLL_MULT 0 1 QA2 QA2# QA3 QA3# QB1 XIN/REF XOUT SER CLK SER DATA MR XTAL OSCILLATOR PLL xM /1 /2 0 1 QB1# QB2 QB2# QB3 FSELB QB3# Pin Configuration (Top View) C Y 2 X P 3 0 6 3 6 V F B G A P IN C O N F IG U R A T IO N T O P V IE W QA1 Q A1# Q A2 6 Q A2# Q A3 Q A3# Q B1 Q B1# 5 VDDA GND GND VDDA 4 GND SER_ DATA Q B2 QB3 VDDB VDDA 3 XO UT SER_ C LK Q B2# Q B3# VDDB NC 2 X IN GND GND VDDA 1 VDDB VDDB GND PLL_ M ULT MR FSELA FSELB VDDA A B C D E F G H www.
DataSheet4U.
net Document #: 38-07725 Rev.
*A Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 8, 2005 PRELIMINARY Pin Definitions Pin # A2 A3 B2,B5,C1,G2,G5,A4 A5,H1,H2,H4,H5 A1,B1,G3,G4 A6 B6 C6 D6 E6 F6 G6 H6 C4 C3 F4 F3 D1 E1 F1 G1 H3 B4 B3 Table 1.
Frequency Table PLL_Mult 0 1 M (PLL Multiplier) x16 x8 Example Input Frequency 19.
44 MHz 19.
53 MHz 19.
44 MHz 19.
53 MHz 38.
88 MHz Pin Name XIN/REF XOUT GND VDDA VDDB QA1 QA1# QA2 QA2# QA3 QA3# QB1 QB1# QB2 QB2# QB3 QB3# MR FSELA FSELB NC Reference Crystal Input or LVTTL Reference Crystal Feedback Ground 3.
3V Power Supply 3.
3V Power Supply LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Reset; Internal Pull-Down, see...

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