PLL103-01 Low Skew Buffers FEATURES Generate 18 copies of High-speed clock inputs.
Supports up to four SDRAM DIMMS synchronous clocks.
• Supports 2-wire I2C serial bus interface with readback.
• 50% duty cycle with low jitter.
• Less than 5ns delay.
www.
DataSheet4U.
com • Skew between any outputs is less than 250 ps.
• Tri-state pin for testing.
• Frequency up to 133 MHZ.
• 3.
0V-3.
7V Supply range.
• 48-pin SSOP package.
• • PIN CONFIGURATION N/C N/C VDD SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 GND BUF_IN VDD SDRAM4 SDRAM5 GND VDD SDRAM6 SDRAM7 GND VDD SDRAM16 GND VDD1 SDATA 1 2 3 4 5 6 7 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N/C N/C VDD SDRAM15 SDRAM14 GND VDD SD...

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