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PLL103-04

Part Number	PLL103-04
Manufacturer	PhaseLink Corporation
Description	1-to-4 Clock Distribution Buffer
Published	Oct 28, 2008
Detailed Description	Preliminary PLL103-04 1-to-4 Clock Distribution Buffer FEATURES 4 outputs identical to FIN. Low skew (< 250 ps between...
Datasheet	PLL103-04 PDF File

Overview

Preliminary PLL103-04 1-to-4 Clock Distribution Buffer FEATURES 4 outputs identical to FIN.
Low skew (< 250 ps between outputs).
Input / Output frequency range 0 – 160 MHz 25mA drive capability at TTL levels.
70mA drive capability at CMOS levels.
Output enable mode available to tri-state all outputs.
www.
DataSheet4U.
com • 3.
3V operation.
• Available in 8-Pin 150mil SOIC.
• • • • • • PIN CONFIGURATION FIN CLK1 CLK2 CLK3 1 8 OE^ VDD GND CLK4 PLL103-04 2 3 4 7 6 5 FIN = 0 ~ 160 Mhz Note: ^: Internal pull-up (30k Ω ) DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs.
It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels.
An output enable selector is available to tri-state all outputs.
BLOCK DIAGRAM OE^ CLK1 FIN CLK2 CLK3 CLK4 47745 Fremont Blvd.
, Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 09/26/00 Page 1 Preliminary PLL10...

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