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PI6LC48P0405

Part Number	PI6LC48P0405
Manufacturer	Pericom Semiconductor
Description	4-Output LVPECL Networking Clock Generator
Published	May 13, 2016
Detailed Description	PI6LC48P0405 4-Output LVPECL Networking Clock Generator Features ÎÎFour differential LVPECL output pairs ÎÎSelectable c...
Datasheet	PI6LC48P0405 PDF File

Overview

PI6LC48P0405 4-Output LVPECL Networking Clock Generator Features ÎÎFour differential LVPECL output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequency: 125MHz ÎÎRMS phase jitter @ 125MHz, using a 25MHz crystal (1.
875MHz – 20MHz): 0.
14ps (typical) ÎÎRMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz – 20MHz): 0.
32ps (typical) ÎÎFull 3.
3V or 2.
5V supply modes ÎÎ-40°C to 85°C operating temperature ÎÎAvailable in lead-free package: 24-TSSOP Description The PI6LC48P0405 is a 4-output LVPECL synthesizer optimized to generate 125MHz clock frequencies and is a member of Pericom’s HiFlex family of high performance clock solutions.
The PI6LC48P0405 uses Pericom’s proprietary low phase noise VCO technology and can achieve less than 0.
32ps typical rms phase jitter, it is ideal for Ethernet interface in all kind of systems.
Applications ÎÎNetworking systems Block Diagram PLL_Bypass XTAL_IN XTAL_OUT Ref_IN IN_SEL OSC M_reset Phase Detector VCO M = 25 (fixed) CLK0 CLK0# ÷5 CLK1 CLK1# CLK2 CLK2# CLK3 CLK3# 15-0118 1 www.
pericom.
com PI6LC48P0405 Rev.
A 09/01/15 Pin Configuration CLK1# CLK1 VDDO CLK0 CLK0# M_reset PLL_Bypass NC VDDA NC VDD NC 1 2 3 4 5 6 7 8 9 10 11 12 24 CLK2# 23 CLK2 22 VDDO 21 CLK3 20 CLK3# 19 GND 18 VDD 17 IN_SEL 16 Ref_IN 15 GND 14 XTAL_IN 13 XTAL_OUT PI6LC48P0405 4-Output LVPECL Networking Clock Generator Pinout Table Pin No.
1, 2 3, 22 4, 5 6 7 8, 10, 12 9 11, 18 13, 14 15, 19 16 17 20, 21 23, 24 Pin Name CLK1#, CLK1 VDDO CLK0, CLK0# M_reset PLL_Bypass NC VDDA VDD XTAL_OUT, XTAL_IN GND Ref_IN IN_SEL CLK3#, CLK3 CLK2, CLK2# I/O Type Output Power Output Input Pulldown Input Pulldown Power Power Output / Input Power Input Pulldown Input Pulldown Output Output Description LVPECL Output Clock 1 Output supply pins LVPECL Output Clock 0 Active HIGH Master Reset.
When logic HIGH, the internal dividers are reset causing the true outputs CLKx to go low a...

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