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PI6LC48L0201

Part Number	PI6LC48L0201
Manufacturer	Pericom Semiconductor
Description	2-Output LVDS Networking Clock Generator
Published	May 13, 2016
Detailed Description	PI6LC48L0201 2-Output LVDS Networking Clock Generator Features ÎÎTwo differential LVDS output pairs ÎÎSelectable crysta...
Datasheet	PI6LC48L0201 PDF File

Overview

PI6LC48L0201 2-Output LVDS Networking Clock Generator Features ÎÎTwo differential LVDS output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 62.
5MHz, 125MHz, 156.
25MHz ÎÎRMS phase jitter @ 156.
25MHz, using a 25MHz crystal (1.
875MHz – 20MHz): 0.
2ps (typical) ÎÎRMS phase jitter @ 156.
25MHz, using a 25MHz crystal (12kHz – 20MHz): 0.
32ps (typical) ÎÎFull 3.
3V or 2.
5V supply modes ÎÎCommercial and industrial ambient operating temperature ÎÎAvailable in lead-free package: 20-TSSOP Description The PI6LC48L0201 is a 2-output LVDS synthesizer optimized to generate Ethernet reference clock frequencies and is a member of Pericom’s HiFlex family of high performance clock solutions.
Using a 25MHz crystal, the most popular Ethernet frequencies can be generated based on the settings of 2 frequency select pins.
The PI6LC48L0201 uses Pericom’s proprietary low phase noise PLL technology to achieve ultra low phase jitter, so it is ideal for Ethernet interface in all kind of systems.
Applications ÎÎNetworking systems Block Diagram XTAL_IN XTAL_OUT Ref_IN IN_SEL OSC M_reset PFD VCO M PLL_ByPass N_SEL[0:1] /N CLK0 CLK0# CLK1 CLK1# 13-0115 1 www.
pericom.
com PI6LC48L0201 Rev.
A 07/23/2013 PI6LC48L0201 2-Output LVDS Networking Clock Generator Pin Configuration NC VDDO CLK0 CLK0# M_reset PLL_ByPass NC VDDA N_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 VDDO 19 CLK1 18 CLK1# 17 GND 16 NC 15 IN_SEL 14 Ref_IN 13 XTAL_IN 12 XTAL_OUT 11 N_SEL1 Pinout Table Pin No.
1, 7, 16 2, 20 3,4 Pin Name NC VDDO CLK0, CLK0# I/O Type Power Output 5 M_reset Input 6 8 9, 11 10 12, 13 14 15 17 18, 19 PLL_ByPass VDDA N_SEL0, N_SEL1 VDD XTAL_OUT, XTAL_IN Ref_IN IN_SEL GND CLK1#, CLK1 Input Power Input Power Crystal Input Input Ground Output - Pull-down Pull-down Pull-down - Description No connection Output Power Supply LVDS Output clock 0 Master reset.
“1”, CLK0CLK1 go to “low”, CLK0#/CLK1# go to “high”; “0” o...

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