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PI6LC48L0201A

Part Number	PI6LC48L0201A
Manufacturer	Pericom Semiconductor
Description	2-Output LVDS Networking Clock Generator
Published	May 13, 2016
Detailed Description	PI6LC48L0201A 2-Output LVDS Networking Clock Generator Features ÎÎTwo differential LVDS output pairs ÎÎSelectable cryst...
Datasheet	PI6LC48L0201A PDF File

Overview

PI6LC48L0201A 2-Output LVDS Networking Clock Generator Features ÎÎTwo differential LVDS output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 62.
5MHz, 125MHz, 156.
25MHz ÎÎRMS phase jitter @ 156.
25MHz, using a 25MHz crystal (12kHz – 20MHz): 0.
3ps (typical) ÎÎRMS phase jitter @ 156.
25MHz, using a 25MHz crystal (12kHz – 20MHz): 0.
5ps (max) ÎÎFull 3.
3V or 2.
5V supply modes ÎÎIndustrial operating temperature ÎÎAvailable in lead-free package: 20-TQFN Description The PI6LC48L0201A is a 2-output LVDS synthesizer optimized to generate Ethernet reference clock frequencies and is a member of Pericom’s HiFlex family of high performance clock solutions.
Using a 25MHz crystal, the most popular Ethernet frequencies can be generated based on the settings of 2 frequency select pins.
The PI6LC48L0201A uses Pericom’s proprietary low phase noise PLL technology to achieve ultra low phase jitter, so it is ideal for Ethernet interface in all kind of systems.
Applications ÎÎNetworking systems Block Diagram XTAL_IN XTAL_OUT Ref_IN IN_SEL OSC M_reset PFD VCO M PLL_ByPass N_SEL[0:1] /N CLK0 CLK0# CLK1 CLK1# 15-0104 1 www.
pericom.
com PI6LC48L0201A Rev.
A 08/04/2015 Pin Configuration VDDO GND CLK0 CLK0# M_reset GND PLL_ByPass GND VDDA N_SEL0 1 2 3 4 20 19 18 17 5 GND 16 6 15 7 14 8 13 9 12 10 11 VDDO CLK1 CLK1# NC IN_SEL Ref_IN XTAL_IN XTAL_OUT PI6LC48L0201A 2-Output LVDS Networking Clock Generator VDD N_SEL1 Pinout Table Pin No.
1, 19 2, 3 Pin Name VDDO CLK0, CLK0# I/O Type Power Output 4 M_reset Input 5, 7, 20 6 8 9, 11 10 12, 13 14 15 16 17, 18 Epad GND PLL_ByPass VDDA N_SEL0, N_SEL1 VDD XTAL_OUT, XTAL_IN Ref_IN IN_SEL NC CLK1#, CLK1 GND Ground Input Power Input Power Crystal Input Input Output Ground - Pull-down Pull-down Pull-down - Description Output Power Supply LVDS Output clock 0 Master reset.
“1”, CLK0CLK1 go to “low”, CLK0#/CLK1# go to “high”; “0” outputs are enab...

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