DatasheetsPDF.com

IS61QDPB21M36A1

ISSI
Part Number IS61QDPB21M36A1
Manufacturer ISSI
Description 36Mb QUADP (Burst 2) Synchronous SRAM
Published Jun 10, 2016
Detailed Description IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) D...
Datasheet PDF File IS61QDPB21M36A1 PDF File

IS61QDPB21M36A1
IS61QDPB21M36A1

Overview
IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP (Burst 2) Synchronous SRAM (2.
5 CYCLE READ LATENCY) DECEMBER 2014 FEATURES  1Mx36 and 2Mx18 configuration available.
 On-chip Delay-Locked Loop (DLL) for wide data valid window.
 Separate independent read and write ports with concurrent read and write operations.
 Synchronous pipeline read with EARLY write operation.
 Double Data Rate (DDR) interface for read and write input ports.
 2.
5 Cycle read latency.
 Fixed 2-bit burst for read and write operations.
 Clock stop support.
 Two input clocks (K and K#) for address and control registering at rising edges only.
 Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
DESCRIPTION The and are synchronous, high- performance CMOS static random access memory (SRAM) devices.
These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write operation, and all internal ope...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)