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IS61QDPB21M36A2

ISSI
Part Number IS61QDPB21M36A2
Manufacturer ISSI
Description 36Mb QUADP (Burst 2) Synchronous SRAM
Published Jun 10, 2016
Detailed Description IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) D...
Datasheet PDF File IS61QDPB21M36A2 PDF File

IS61QDPB21M36A2
IS61QDPB21M36A2


Overview
IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP (Burst 2) Synchronous SRAM (2.
5 CYCLE READ LATENCY) DECEMBER 2014 FEATURES  1Mx36 and 2Mx18 configuration available.
 On-chip Delay-Locked Loop (DLL) for wide data valid window.
 Separate independent read and write ports with concurrent read and write operations.
 Synchronous pipeline read with EARLY write operation.
 Double Data Rate (DDR) interface for read and write input ports.
 2.
5 Cycle read latency.
 Fixed 2-bit burst for read and write operations.
 Clock stop support.
 Two input clocks (K and K#) for address and control registering at rising edges only.
 Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
DESCRIPTION The and are synchronous, high- performance CMOS static random access memory (SRAM) devices.
These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
Refer to the for a description of the basic operations of these SRAMs.
Read and write addresses are registered on alternating rising edges of the K clock.
Read and write performed in double data rate.
The following are registered internally on the rising edge of the K clock:  Read address  Read enable  Write enable  Data valid pin (QVLD).
 Data-in for early writes  +1.
8V core power supply and 1.
5, 1.
8V VDDQ, used with 0.
75, 0.
9V VREF.
 HSTL input and output interface.
 Registered addresses, write and read controls, byte writes, data in, and data outputs.
 Full data coherency.
The following are registered on the rising edge of the K# clock:  Write address  Byte writes  Data-in for second burst addresses  Boundary scan using limited set of JTAG 1149.
1 functions.
 Byte Write capability.
 Fine ball grid array (FBGA) package option: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array  Programmable impedance output drivers via 5x user...


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