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74HCT193

NXP
Part Number 74HCT193
Manufacturer NXP
Description Presettable synchronous 4-bit binary up/down counter
Published Jun 21, 2016
Detailed Description 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Rev. 5 — 29 January 2016 Product data sheet 1...
Datasheet PDF File 74HCT193 PDF File

74HCT193
74HCT193


Overview
74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Rev.
5 — 29 January 2016 Product data sheet 1.
General description The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter.
Separate up/down clocks, CPU and CPD respectively, simplify operation.
The outputs change state synchronously with the LOW-to-HIGH transition of either clock input.
If the CPU clock is pulsed while CPD is held HIGH, the device will count up.
If the CPD clock is pulsed while CPU is held HIGH, the device will count down.
Only one clock input can be held HIGH at any time to guarantee predictable behavior.
The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL).
The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH.
When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.
TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock.
Likewise, the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW.
The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms.
Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added.
The counter may be preset by the asynchronous parallel load capability of the circuit.
Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW.
A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to Q3) LOW.
If one of the clock inputs is LOW during and after a reset or load operation, t...


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