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74HCT107

Philips
Part Number 74HCT107
Manufacturer Philips
Description Dual JK flip-flop
Published May 28, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Fam...
Datasheet PDF File 74HCT107 PDF File

74HCT107
74HCT107

Overview
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT107 Dual JK flip-flop with reset; negative-edge trigger Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger FEATURES • Output capability: standard • ICC category: flip-flops GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no.
7A.
74HC/HCT107 The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay nCP to nQ nCP to nQ nR to nQ, nQ fmax CI CPD Notes 1.
CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2.
For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.
5 V.
ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”.
maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1...


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