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CY7C1011G

Cypress
Part Number CY7C1011G
Manufacturer Cypress
Description 2-Mbit (128K words x 16 bit) Static RAM
Published Oct 2, 2016
Detailed Description CY7C1011G Automotive 2-Mbit (128K words × 16 bit) Static RAM with Error-Correcting Code (ECC) 2-Mbit (128K words × 16 b...
Datasheet PDF File CY7C1011G PDF File

CY7C1011G
CY7C1011G

Overview
CY7C1011G Automotive 2-Mbit (128K words × 16 bit) Static RAM with Error-Correcting Code (ECC) 2-Mbit (128K words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features ■ High speed ❐ tAA = 10 ns ■ Temperature range ❐ Automotive-A: –40 °C to 85 °C ❐ Automotive-E: –40 °C to 125 °C ■ Embedded correction[1] error-correcting code (ECC) for single-bit error ■ Low active and standby current ❐ Active current, ICC = 40-mA typical (Automotive-E) ❐ Standby current, ISB2 = 6-mA typical (Automotive-E) ■ Operating voltage range: 2.
2 V to 3.
6 V ■ 1.
0-V data retention ■ TTL compatible inputs and outputs ■ Available in Pb-free 48-ball VFBGA and 44-pin TSOP II packages Functional Description CY7C1011G is a high-performance CMOS fast static RAM automotive part with embedded ECC.
This device has a single Chip Enable (CE) input, and is accessed by asserting it LOW.
To perform data writes, assert the Write Enable (WE) input LOW, and provide the data on the device data pins (I/O0 through I/O15) and address pins (A0 through A16) pins.
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control byte writes and write data on the corresponding I/O lines to the memory location specified.
BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.
To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines.
You can access read data on the I/O lines (I/O0 through I/O15).
To perform byte access, assert the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE LOW), or when the control signals are deasserted (OE, BLE, BHE).
Logic Block Diagram – CY7C1011G ECC ENCODER INPUT BUFFER ROW  DECODER SENSE  AMPLIFIERS ECC DECODER A0 A1 A2 A3 A4 MEMORY A5 ARRAY A6 A7 A8 A9 COLUMN DECODER I/O0‐I/O7 I/O8‐I/O15 A10 A11 A12 ...


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